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PU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

DATA

OD

PUP

PDN

IE

CR


DATA

PU Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4 PU5

PU0 : PU0
bits : 0 - 0 (1 bit)
access : read-write

PU1 : PU1
bits : 1 - 1 (1 bit)
access : read-write

PU2 : PU2
bits : 2 - 2 (1 bit)
access : read-write

PU3 : PU3
bits : 3 - 3 (1 bit)
access : read-write

PU4 : PU4
bits : 4 - 4 (1 bit)
access : read-write

PU5 : PU5
bits : 5 - 5 (1 bit)
access : read-write


OD

PU Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0OD PU1OD PU2OD PU3OD PU4OD PU5OD

PU0OD : PU0OD
bits : 0 - 0 (1 bit)
access : read-write

PU1OD : PU1OD
bits : 1 - 1 (1 bit)
access : read-write

PU2OD : PU2OD
bits : 2 - 2 (1 bit)
access : read-write

PU3OD : PU3OD
bits : 3 - 3 (1 bit)
access : read-write

PU4OD : PU4OD
bits : 4 - 4 (1 bit)
access : read-write

PU5OD : PU5OD
bits : 5 - 5 (1 bit)
access : read-write


PUP

PU Pull-Up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0UP PU1UP PU2UP PU3UP PU4UP PU5UP

PU0UP : PU0UP
bits : 0 - 0 (1 bit)
access : read-write

PU1UP : PU1UP
bits : 1 - 1 (1 bit)
access : read-write

PU2UP : PU2UP
bits : 2 - 2 (1 bit)
access : read-write

PU3UP : PU3UP
bits : 3 - 3 (1 bit)
access : read-write

PU4UP : PU4UP
bits : 4 - 4 (1 bit)
access : read-write

PU5UP : PU5UP
bits : 5 - 5 (1 bit)
access : read-write


PDN

PU Pull-Down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDN PDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0DN PU1DN PU2DN PU3DN PU4DN PU5DN

PU0DN : PU0DN
bits : 0 - 0 (1 bit)
access : read-write

PU1DN : PU1DN
bits : 1 - 1 (1 bit)
access : read-write

PU2DN : PU2DN
bits : 2 - 2 (1 bit)
access : read-write

PU3DN : PU3DN
bits : 3 - 3 (1 bit)
access : read-write

PU4DN : PU4DN
bits : 4 - 4 (1 bit)
access : read-write

PU5DN : PU5DN
bits : 5 - 5 (1 bit)
access : read-write


IE

PU Input Enable Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0IE PU1IE PU2IE PU3IE PU4IE PU5IE

PU0IE : PU0IE
bits : 0 - 0 (1 bit)
access : read-write

PU1IE : PU1IE
bits : 1 - 1 (1 bit)
access : read-write

PU2IE : PU2IE
bits : 2 - 2 (1 bit)
access : read-write

PU3IE : PU3IE
bits : 3 - 3 (1 bit)
access : read-write

PU4IE : PU4IE
bits : 4 - 4 (1 bit)
access : read-write

PU5IE : PU5IE
bits : 5 - 5 (1 bit)
access : read-write


CR

PU Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0C PU1C PU2C PU3C PU4C PU5C

PU0C : PU0C
bits : 0 - 0 (1 bit)
access : read-write

PU1C : PU1C
bits : 1 - 1 (1 bit)
access : read-write

PU2C : PU2C
bits : 2 - 2 (1 bit)
access : read-write

PU3C : PU3C
bits : 3 - 3 (1 bit)
access : read-write

PU4C : PU4C
bits : 4 - 4 (1 bit)
access : read-write

PU5C : PU5C
bits : 5 - 5 (1 bit)
access : read-write



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