\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x8 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
PU Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : PU0
bits : 0 - 0 (1 bit)
access : read-write
PU1 : PU1
bits : 1 - 1 (1 bit)
access : read-write
PU2 : PU2
bits : 2 - 2 (1 bit)
access : read-write
PU3 : PU3
bits : 3 - 3 (1 bit)
access : read-write
PU4 : PU4
bits : 4 - 4 (1 bit)
access : read-write
PU5 : PU5
bits : 5 - 5 (1 bit)
access : read-write
PU Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0OD : PU0OD
bits : 0 - 0 (1 bit)
access : read-write
PU1OD : PU1OD
bits : 1 - 1 (1 bit)
access : read-write
PU2OD : PU2OD
bits : 2 - 2 (1 bit)
access : read-write
PU3OD : PU3OD
bits : 3 - 3 (1 bit)
access : read-write
PU4OD : PU4OD
bits : 4 - 4 (1 bit)
access : read-write
PU5OD : PU5OD
bits : 5 - 5 (1 bit)
access : read-write
PU Pull-Up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0UP : PU0UP
bits : 0 - 0 (1 bit)
access : read-write
PU1UP : PU1UP
bits : 1 - 1 (1 bit)
access : read-write
PU2UP : PU2UP
bits : 2 - 2 (1 bit)
access : read-write
PU3UP : PU3UP
bits : 3 - 3 (1 bit)
access : read-write
PU4UP : PU4UP
bits : 4 - 4 (1 bit)
access : read-write
PU5UP : PU5UP
bits : 5 - 5 (1 bit)
access : read-write
PU Pull-Down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0DN : PU0DN
bits : 0 - 0 (1 bit)
access : read-write
PU1DN : PU1DN
bits : 1 - 1 (1 bit)
access : read-write
PU2DN : PU2DN
bits : 2 - 2 (1 bit)
access : read-write
PU3DN : PU3DN
bits : 3 - 3 (1 bit)
access : read-write
PU4DN : PU4DN
bits : 4 - 4 (1 bit)
access : read-write
PU5DN : PU5DN
bits : 5 - 5 (1 bit)
access : read-write
PU Input Enable Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0IE : PU0IE
bits : 0 - 0 (1 bit)
access : read-write
PU1IE : PU1IE
bits : 1 - 1 (1 bit)
access : read-write
PU2IE : PU2IE
bits : 2 - 2 (1 bit)
access : read-write
PU3IE : PU3IE
bits : 3 - 3 (1 bit)
access : read-write
PU4IE : PU4IE
bits : 4 - 4 (1 bit)
access : read-write
PU5IE : PU5IE
bits : 5 - 5 (1 bit)
access : read-write
PU Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0C : PU0C
bits : 0 - 0 (1 bit)
access : read-write
PU1C : PU1C
bits : 1 - 1 (1 bit)
access : read-write
PU2C : PU2C
bits : 2 - 2 (1 bit)
access : read-write
PU3C : PU3C
bits : 3 - 3 (1 bit)
access : read-write
PU4C : PU4C
bits : 4 - 4 (1 bit)
access : read-write
PU5C : PU5C
bits : 5 - 5 (1 bit)
access : read-write
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