\n

PV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x2C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

DATA

PUP

PDN

IE


DATA

PV Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0 PV1 PV2 PV3

PV0 : PV0
bits : 0 - 0 (1 bit)
access : read-only

PV1 : PV1
bits : 1 - 1 (1 bit)
access : read-only

PV2 : PV2
bits : 2 - 2 (1 bit)
access : read-only

PV3 : PV3
bits : 3 - 3 (1 bit)
access : read-only


PUP

PV Pull-Up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0UP PV1UP PV2UP PV3UP

PV0UP : PV0UP
bits : 0 - 0 (1 bit)
access : read-only

PV1UP : PV1UP
bits : 1 - 1 (1 bit)
access : read-only

PV2UP : PV2UP
bits : 2 - 2 (1 bit)
access : read-only

PV3UP : PV3UP
bits : 3 - 3 (1 bit)
access : read-only


PDN

PV Pull-Down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDN PDN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0DN PV1DN PV2DN PV3DN

PV0DN : PV0DN
bits : 0 - 0 (1 bit)
access : read-only

PV1DN : PV1DN
bits : 1 - 1 (1 bit)
access : read-only

PV2DN : PV2DN
bits : 2 - 2 (1 bit)
access : read-only

PV3DN : PV3DN
bits : 3 - 3 (1 bit)
access : read-only


IE

PV Input Enable Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IE IE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PV0IE PV1IE PV2IE PV3IE

PV0IE : PV0IE
bits : 0 - 0 (1 bit)
access : read-only

PV1IE : PV1IE
bits : 1 - 1 (1 bit)
access : read-only

PV2IE : PV2IE
bits : 2 - 2 (1 bit)
access : read-only

PV3IE : PV3IE
bits : 3 - 3 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.