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TB3

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :

Registers

EN_A

EN_B

FFCR_A

FFCR_B

ST_A

ST_B

IM_A

IM_B

UC_A

UC_B

RG0_A

RG0_B

RG1_A

RG1_B

CP0_A

CP0_B

CP1_A

CP1_B

RUN_A

RUN_B

CR_A

CR_B

MOD_A

MOD_B


EN_A

TB Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN_A EN_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBHALT TBEN

TBHALT : TBHALT
bits : 6 - 6 (1 bit)
access : read-write

TBEN : TBEN
bits : 7 - 7 (1 bit)
access : read-write


EN_B

TB Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN_B EN_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBHALT TBEN

TBHALT : TBHALT
bits : 6 - 6 (1 bit)
access : read-write

TBEN : TBEN
bits : 7 - 7 (1 bit)
access : read-write


FFCR_A

TB Flip-Flop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FFCR_A FFCR_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBFF0C TBE0T1 TBE1T1 TBC0T1 TBC1T1

TBFF0C : TBFF0C
bits : 0 - 1 (2 bit)
access : read-write

TBE0T1 : TBE0T1
bits : 2 - 2 (1 bit)
access : read-write

TBE1T1 : TBE1T1
bits : 3 - 3 (1 bit)
access : read-write

TBC0T1 : TBC0T1
bits : 4 - 4 (1 bit)
access : read-write

TBC1T1 : TBC1T1
bits : 5 - 5 (1 bit)
access : read-write


FFCR_B

TB Flip-Flop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FFCR_B FFCR_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBFF0C TBE0T1 TBE1T1 TBC0T1 TBC1T1

TBFF0C : TBFF0C
bits : 0 - 1 (2 bit)
access : read-write

TBE0T1 : TBE0T1
bits : 2 - 2 (1 bit)
access : read-write

TBE1T1 : TBE1T1
bits : 3 - 3 (1 bit)
access : read-write

TBC0T1 : TBC0T1
bits : 4 - 4 (1 bit)
access : read-write

TBC1T1 : TBC1T1
bits : 5 - 5 (1 bit)
access : read-write


ST_A

TB Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ST_A ST_A read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTTB0 INTTB1 INTTBOF

INTTB0 : INTTB0
bits : 0 - 0 (1 bit)
access : read-only

INTTB1 : INTTB1
bits : 1 - 1 (1 bit)
access : read-only

INTTBOF : INTTBOF
bits : 2 - 2 (1 bit)
access : read-only


ST_B

TB Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ST_B ST_B read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTTB0 INTTB1 INTTBOF

INTTB0 : INTTB0
bits : 0 - 0 (1 bit)
access : read-only

INTTB1 : INTTB1
bits : 1 - 1 (1 bit)
access : read-only

INTTBOF : INTTBOF
bits : 2 - 2 (1 bit)
access : read-only


IM_A

TB Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM_A IM_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBIM0 TBIM1 TBIMOF

TBIM0 : TBIM0
bits : 0 - 0 (1 bit)
access : read-write

TBIM1 : TBIM1
bits : 1 - 1 (1 bit)
access : read-write

TBIMOF : TBIMOF
bits : 2 - 2 (1 bit)
access : read-write


IM_B

TB Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM_B IM_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBIM0 TBIM1 TBIMOF

TBIM0 : TBIM0
bits : 0 - 0 (1 bit)
access : read-write

TBIM1 : TBIM1
bits : 1 - 1 (1 bit)
access : read-write

TBIMOF : TBIMOF
bits : 2 - 2 (1 bit)
access : read-write


UC_A

TB Read Capture Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UC_A UC_A read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBUC

TBUC : TBUC
bits : 0 - 15 (16 bit)
access : read-only


UC_B

TB Read Capture Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UC_B UC_B read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBUC

TBUC : TBUC
bits : 0 - 15 (16 bit)
access : read-only


RG0_A

TB RG0 Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0_A RG0_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRG0

TBRG0 : TBRG0
bits : 0 - 15 (16 bit)
access : read-write


RG0_B

TB RG0 Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0_B RG0_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRG0

TBRG0 : TBRG0
bits : 0 - 15 (16 bit)
access : read-write


RG1_A

TB RG1 Timer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1_A RG1_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRG1

TBRG1 : TBRG1
bits : 0 - 15 (16 bit)
access : read-write


RG1_B

TB RG1 Timer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1_B RG1_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRG1

TBRG1 : TBRG1
bits : 0 - 15 (16 bit)
access : read-write


CP0_A

TB CP0 Capture Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0_A CP0_A read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCP0

TBCP0 : TBCP0
bits : 0 - 15 (16 bit)
access : read-only


CP0_B

TB CP0 Capture Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0_B CP0_B read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCP0

TBCP0 : TBCP0
bits : 0 - 15 (16 bit)
access : read-only


CP1_A

TB CP1 Capture Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP1_A CP1_A read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCP1

TBCP1 : TBCP1
bits : 0 - 15 (16 bit)
access : read-only


CP1_B

TB CP1 Capture Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP1_B CP1_B read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCP1

TBCP1 : TBCP1
bits : 0 - 15 (16 bit)
access : read-only


RUN_A

TB RUN Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUN_A RUN_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRUN TBPRUN

TBRUN : TBRUN
bits : 0 - 0 (1 bit)
access : read-write

TBPRUN : TBPRUN
bits : 2 - 2 (1 bit)
access : read-write


RUN_B

TB RUN Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUN_B RUN_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBRUN TBPRUN

TBRUN : TBRUN
bits : 0 - 0 (1 bit)
access : read-write

TBPRUN : TBPRUN
bits : 2 - 2 (1 bit)
access : read-write


CR_A

TB Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR_A CR_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSSEL TRGSEL I2TB TBSYNC TBWBF

CSSEL : CSSEL
bits : 0 - 0 (1 bit)
access : read-write

TRGSEL : TRGSEL
bits : 1 - 1 (1 bit)
access : read-write

I2TB : I2TB
bits : 3 - 3 (1 bit)
access : read-write

TBSYNC : TBSYNC
bits : 5 - 5 (1 bit)
access : read-write

TBWBF : TBWBF
bits : 7 - 7 (1 bit)
access : read-write


CR_B

TB Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR_B CR_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSSEL TRGSEL I2TB TBSYNC TBWBF

CSSEL : CSSEL
bits : 0 - 0 (1 bit)
access : read-write

TRGSEL : TRGSEL
bits : 1 - 1 (1 bit)
access : read-write

I2TB : I2TB
bits : 3 - 3 (1 bit)
access : read-write

TBSYNC : TBSYNC
bits : 5 - 5 (1 bit)
access : read-write

TBWBF : TBWBF
bits : 7 - 7 (1 bit)
access : read-write


MOD_A

TB Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD_A MOD_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCLK TBCLE TBCPM TBCP TBRSWR

TBCLK : TBCLK
bits : 0 - 1 (2 bit)
access : read-write

TBCLE : TBCLE
bits : 2 - 2 (1 bit)
access : read-write

TBCPM : TBCPM
bits : 3 - 4 (2 bit)
access : read-write

TBCP : TBCP
bits : 5 - 5 (1 bit)
access : write-only

TBRSWR : TBRSWR
bits : 6 - 6 (1 bit)
access : read-write


MOD_B

TB Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD_B MOD_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBCLK TBCLE TBCPM TBCP TBRSWR

TBCLK : TBCLK
bits : 0 - 1 (2 bit)
access : read-write

TBCLE : TBCLE
bits : 2 - 2 (1 bit)
access : read-write

TBCPM : TBCPM
bits : 3 - 4 (2 bit)
access : read-write

TBCP : TBCP
bits : 5 - 5 (1 bit)
access : write-only

TBRSWR : TBRSWR
bits : 6 - 6 (1 bit)
access : read-write



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