\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
Two-phase Pulse Input Count Run Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHCRUN : PHCRUN
bits : 0 - 0 (1 bit)
access : read-write
Two-phase Pulse Input Count Compare Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHCCMP0 : PHCCMP0
bits : 0 - 15 (16 bit)
access : read-write
Two-phase Pulse Input Count Compare Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHCCMP1 : PHCCMP1
bits : 0 - 15 (16 bit)
access : read-write
Two-phase Pulse Input Count Counter Read Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PHCCNT : PHCCNT
bits : 0 - 15 (16 bit)
access : read-only
Two-phase Pulse Input Count Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHCMD : PHCMD
bits : 0 - 0 (1 bit)
access : read-write
NFOFF : NFOFF
bits : 1 - 1 (1 bit)
access : read-write
CMP0EN : CMP0EN
bits : 2 - 2 (1 bit)
access : read-write
CMP1EN : CMP1EN
bits : 3 - 3 (1 bit)
access : read-write
EVRYINT : EVRYINT
bits : 4 - 4 (1 bit)
access : read-write
Two-phase Pulse Input Count Timer Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHCEN : PHCEN
bits : 0 - 0 (1 bit)
access : read-write
Two-phase Pulse Input Count Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0 : CMP0
bits : 0 - 0 (1 bit)
access : read-write
CMP1 : CMP1
bits : 1 - 1 (1 bit)
access : read-write
OVF : OVF
bits : 2 - 2 (1 bit)
access : read-write
UDF : UDF
bits : 3 - 3 (1 bit)
access : read-write
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