\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write
PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write
FPSEL : FPSEL
bits : 12 - 12 (1 bit)
access : read-write
SCOSEL : SCOSEL
bits : 16 - 17 (2 bit)
access : read-write
System Clock Selection Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCKFLG : SYSCKFLG
bits : 0 - 0 (1 bit)
access : read-only
SYSCK : SYSCK
bits : 1 - 1 (1 bit)
access : read-write
Timer D Clock Setting Registe
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICRCG0 : ICRCG0
bits : 0 - 0 (1 bit)
access : write-only
ICRCG1 : ICRCG1
bits : 1 - 1 (1 bit)
access : write-only
ICRCG2 : ICRCG2
bits : 2 - 2 (1 bit)
access : write-only
ICRCG3 : ICRCG3
bits : 3 - 3 (1 bit)
access : write-only
ICRCG4 : ICRCG4
bits : 4 - 4 (1 bit)
access : write-only
NMI status flag register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMIFLG0 : NMIFLG0
bits : 0 - 0 (1 bit)
access : read-only
NMIFLG1 : NMIFLG1
bits : 1 - 1 (1 bit)
access : read-only
Reset Flash register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PONRSTF : PONRSTF
bits : 0 - 0 (1 bit)
access : read-write
PINRSTF : PINRSTF
bits : 1 - 1 (1 bit)
access : read-write
WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write
SYSRSTF : SYSRSTF
bits : 4 - 4 (1 bit)
access : read-write
OFDRSTF : OFDRSTF
bits : 5 - 5 (1 bit)
access : read-write
CG Interrupt Mode Control Register A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT0EN : INT0EN
bits : 0 - 0 (1 bit)
access : read-write
EMST0 : EMST0
bits : 2 - 3 (2 bit)
access : read-only
EMCG0 : EMCG0
bits : 4 - 6 (3 bit)
access : read-write
INT1EN : INT1EN
bits : 8 - 8 (1 bit)
access : read-write
EMST1 : EMST1
bits : 10 - 11 (2 bit)
access : read-only
EMCG1 : EMCG1
bits : 12 - 14 (3 bit)
access : read-write
INT2EN : INT2EN
bits : 16 - 16 (1 bit)
access : read-write
EMST2 : EMST2
bits : 18 - 19 (2 bit)
access : read-only
EMCG2 : EMCG2
bits : 20 - 22 (3 bit)
access : read-write
INT3EN : INT3EN
bits : 24 - 24 (1 bit)
access : read-write
EMST3 : EMST3
bits : 26 - 27 (2 bit)
access : read-only
EMCG3 : EMCG3
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Mode Control Register B
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT4EN : INT4EN
bits : 0 - 0 (1 bit)
access : read-write
EMST4 : EMST4
bits : 2 - 3 (2 bit)
access : read-only
EMCG4 : EMCG4
bits : 4 - 6 (3 bit)
access : read-write
INT5EN : INT5EN
bits : 8 - 8 (1 bit)
access : read-write
EMST5 : EMST5
bits : 10 - 11 (2 bit)
access : read-only
EMCG5 : EMCG5
bits : 12 - 14 (3 bit)
access : read-write
INT6EN : INT6EN
bits : 16 - 16 (1 bit)
access : read-write
EMST6 : EMST6
bits : 18 - 19 (2 bit)
access : read-only
EMCG6 : EMCG6
bits : 20 - 22 (3 bit)
access : read-write
INT7EN : INT7EN
bits : 24 - 24 (1 bit)
access : read-write
EMST7 : EMST7
bits : 26 - 27 (2 bit)
access : read-only
EMCG7 : EMCG7
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Mode Control Register C
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8EN : INT8EN
bits : 0 - 0 (1 bit)
access : read-write
EMST8 : EMST8
bits : 2 - 3 (2 bit)
access : read-only
EMCG8 : EMCG8
bits : 4 - 6 (3 bit)
access : read-write
INT9EN : INT9EN
bits : 8 - 8 (1 bit)
access : read-write
EMST9 : EMST9
bits : 10 - 11 (2 bit)
access : read-only
EMCG9 : EMCG9
bits : 12 - 14 (3 bit)
access : read-write
INTAEN : INTAEN
bits : 16 - 16 (1 bit)
access : read-write
EMSTA : EMSTA
bits : 18 - 19 (2 bit)
access : read-only
EMCGA : EMCGA
bits : 20 - 22 (3 bit)
access : read-write
INTBEN : INTBEN
bits : 24 - 24 (1 bit)
access : read-write
EMSTB : EMSTB
bits : 26 - 27 (2 bit)
access : read-only
EMCGB : EMCGB
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Mode Control Register D
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTCEN : INTCEN
bits : 0 - 0 (1 bit)
access : read-write
EMSTC : EMSTC
bits : 2 - 3 (2 bit)
access : read-only
EMCGC : EMCGC
bits : 4 - 6 (3 bit)
access : read-write
INTDEN : INTDEN
bits : 8 - 8 (1 bit)
access : read-write
EMSTD : EMSTD
bits : 10 - 11 (2 bit)
access : read-only
EMCGD : EMCGD
bits : 12 - 14 (3 bit)
access : read-write
INTEEN : INTEEN
bits : 16 - 16 (1 bit)
access : read-write
EMSTE : EMSTE
bits : 18 - 19 (2 bit)
access : read-only
EMCGE : EMCGE
bits : 20 - 22 (3 bit)
access : read-write
INTFEN : INTFEN
bits : 24 - 24 (1 bit)
access : read-write
EMSTF : EMSTF
bits : 26 - 27 (2 bit)
access : read-only
EMCGF : EMCGF
bits : 28 - 30 (3 bit)
access : read-write
CG Interrupt Mode Control Register E
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT10EN : INT10EN
bits : 0 - 0 (1 bit)
access : read-write
EMST10 : EMST10
bits : 2 - 3 (2 bit)
access : read-only
EMCG10 : EMCG10
bits : 4 - 6 (3 bit)
access : read-write
INT11EN : INT11EN
bits : 8 - 8 (1 bit)
access : read-write
EMST11 : EMST11
bits : 10 - 11 (2 bit)
access : read-only
EMCG11 : EMCG11
bits : 12 - 14 (3 bit)
access : read-write
INT12EN : INT12EN
bits : 16 - 16 (1 bit)
access : read-write
EMST12 : EMST12
bits : 18 - 19 (2 bit)
access : read-only
EMCG12 : EMCG12
bits : 20 - 22 (3 bit)
access : read-write
INT13EN : INT13EN
bits : 24 - 24 (1 bit)
access : read-write
EMST13 : EMST13
bits : 26 - 27 (2 bit)
access : read-only
EMCG13 : EMCG13
bits : 28 - 30 (3 bit)
access : read-write
Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUEON : WUEON
bits : 0 - 0 (1 bit)
access : write-only
WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only
WUPSEL : WUPSEL
bits : 3 - 3 (1 bit)
access : read-write
XEN : XEN
bits : 8 - 8 (1 bit)
access : read-write
WUDOR_L : WUDOR_L
bits : 14 - 15 (2 bit)
access : read-write
XEN2 : XEN2
bits : 16 - 16 (1 bit)
access : read-write
OSCSEL : OSCSEL
bits : 17 - 17 (1 bit)
access : read-write
WUDOR_M : WUDOR_M
bits : 20 - 23 (4 bit)
access : read-write
WUODR_H : WUODR_H
bits : 24 - 31 (8 bit)
access : read-write
Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write
RXEN : RXEN
bits : 8 - 8 (1 bit)
access : read-write
DRVE : DRVE
bits : 16 - 16 (1 bit)
access : read-write
SDFLASH : SDFLASH
bits : 18 - 18 (1 bit)
access : read-write
ISOFLASH : ISOFLASH
bits : 19 - 19 (1 bit)
access : read-write
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