\n

PU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x14 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

DATA

FR4

FR5

OD

PUP

PDN

IE

CR

FR1

FR2


DATA

Port U Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4 PU5 PU6

PU4 : PU4
bits : 4 - 4 (1 bit)
access : read-write

PU5 : PU5
bits : 5 - 5 (1 bit)
access : read-write

PU6 : PU6
bits : 6 - 6 (1 bit)
access : read-write


FR4

Port U Function Register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR4 FR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4F4 PU5F4

PU4F4 : PU4F4
bits : 4 - 4 (1 bit)
access : read-write

PU5F4 : PU5F4
bits : 5 - 5 (1 bit)
access : read-write


FR5

Port U Function Register 5
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR5 FR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4F5

PU4F5 : PU4F5
bits : 4 - 4 (1 bit)
access : read-write


OD

Port U Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4OD PU5OD PU6OD

PU4OD : PU4OD
bits : 4 - 4 (1 bit)
access : read-write

PU5OD : PU5OD
bits : 5 - 5 (1 bit)
access : read-write

PU6OD : PU6OD
bits : 6 - 6 (1 bit)
access : read-write


PUP

Port U Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4UP PU5UP PU6UP

PU4UP : PU4UP
bits : 4 - 4 (1 bit)
access : read-write

PU5UP : PU5UP
bits : 5 - 5 (1 bit)
access : read-write

PU6UP : PU6UP
bits : 6 - 6 (1 bit)
access : read-write


PDN

Port U Pull-down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDN PDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4DN PU5DN PU6DN

PU4DN : PU4DN
bits : 4 - 4 (1 bit)
access : read-write

PU5DN : PU5DN
bits : 5 - 5 (1 bit)
access : read-write

PU6DN : PU6DN
bits : 6 - 6 (1 bit)
access : read-write


IE

Port U Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4IE PU5IE PU6IE

PU4IE : PU4IE
bits : 4 - 4 (1 bit)
access : read-write

PU5IE : PU5IE
bits : 5 - 5 (1 bit)
access : read-write

PU6IE : PU6IE
bits : 6 - 6 (1 bit)
access : read-write


CR

Port U Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4C PU5C PU6C

PU4C : PU4C
bits : 4 - 4 (1 bit)
access : read-write

PU5C : PU5C
bits : 5 - 5 (1 bit)
access : read-write

PU6C : PU6C
bits : 6 - 6 (1 bit)
access : read-write


FR1

Port U Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR1 FR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU4F1 PU5F1 PU6F1

PU4F1 : PU4F1
bits : 4 - 4 (1 bit)
access : read-write

PU5F1 : PU5F1
bits : 5 - 5 (1 bit)
access : read-write

PU6F1 : PU6F1
bits : 6 - 6 (1 bit)
access : read-write


FR2

Port U Function Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR2 FR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU5F2 PU6F2

PU5F2 : PU5F2
bits : 5 - 5 (1 bit)
access : read-write

PU6F2 : PU6F2
bits : 6 - 6 (1 bit)
access : read-write



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