\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x4 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x40 Bytes (0x0)
size : 0xC4 byte (0x0)
mem_usage : registers
protection :
T32A Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE32 : MODE32
bits : 0 - 0 (1 bit)
access : read-write
HALT : HALT
bits : 1 - 1 (1 bit)
access : read-write
T32A Compare Register C1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRGC1 : CRGC1
bits : 0 - 31 (32 bit)
access : read-only
T32A Run Register A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUNA : RUNA
bits : 0 - 0 (1 bit)
access : read-write
SFTSTAA : SFTSTAA
bits : 1 - 1 (1 bit)
access : write-only
SFTSTPA : SFTSTPA
bits : 2 - 2 (1 bit)
access : write-only
RUNFLGA : RUNFLGA
bits : 4 - 4 (1 bit)
access : read-only
T32A Control Register A
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTA : STARTA
bits : 0 - 2 (3 bit)
access : read-write
STOPA : STOPA
bits : 4 - 6 (3 bit)
access : read-write
RELDA : RELDA
bits : 8 - 10 (3 bit)
access : read-write
UPDNA : UPDNA
bits : 16 - 17 (2 bit)
access : read-write
WBFA : WBFA
bits : 20 - 20 (1 bit)
access : read-write
CLKA : CLKA
bits : 24 - 26 (3 bit)
access : read-write
PRSCLA : PRSCLA
bits : 28 - 30 (3 bit)
access : read-write
T32A Capture Control Register A
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPMA0 : CAPMA0
bits : 0 - 2 (3 bit)
access : read-write
CAPMA1 : CAPMA1
bits : 4 - 6 (3 bit)
access : read-write
T32A Output Control Register A0
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OCRA : OCRA
bits : 0 - 1 (2 bit)
access : write-only
T32A Output Control Register A1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCRCMPA0 : OCRCMPA0
bits : 0 - 1 (2 bit)
access : read-write
OCRCMPA1 : OCRCMPA1
bits : 2 - 3 (2 bit)
access : read-write
OCRCAPA0 : OCRCAPA0
bits : 4 - 5 (2 bit)
access : read-write
OCRCAPA1 : OCRCAPA1
bits : 6 - 7 (2 bit)
access : read-write
T32A Status Register A
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTA0 : INTA0
bits : 0 - 0 (1 bit)
access : read-write
INTA1 : INTA1
bits : 1 - 1 (1 bit)
access : read-write
INTOFA : INTOFA
bits : 2 - 2 (1 bit)
access : read-write
INTUFA : INTUFA
bits : 3 - 3 (1 bit)
access : read-write
T32A Interrupt Mask Register A
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMA0 : IMA0
bits : 0 - 0 (1 bit)
access : read-write
IMA1 : IMA1
bits : 1 - 1 (1 bit)
access : read-write
IMOFA : IMOFA
bits : 2 - 2 (1 bit)
access : read-write
IMUFA : IMUFA
bits : 3 - 3 (1 bit)
access : read-write
T32A Counter Capture Register A
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMRA : TMRA
bits : 0 - 15 (16 bit)
access : read-only
T32A Reload Register A
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELDA : RELDA
bits : 0 - 15 (16 bit)
access : read-write
T32A Timer Register A0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGA0 : RGA0
bits : 0 - 15 (16 bit)
access : read-write
T32A Timer Register A1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGA1 : RGA1
bits : 0 - 15 (16 bit)
access : read-write
T32A Capture Register A0
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPA0 : CAPA0
bits : 0 - 15 (16 bit)
access : read-only
T32A Capture Register A1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPA1 : CAPA1
bits : 0 - 15 (16 bit)
access : read-only
T32A DMA Request Enable Register A
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAENA0 : DMAENA0
bits : 0 - 0 (1 bit)
access : read-write
DMAENA1 : DMAENA1
bits : 1 - 1 (1 bit)
access : read-write
DMAENA2 : DMAENA2
bits : 2 - 2 (1 bit)
access : read-write
T32A Compare Register A0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRGA0 : CRGA0
bits : 0 - 15 (16 bit)
access : read-only
T32A Compare Register A1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRGA1 : CRGA1
bits : 0 - 15 (16 bit)
access : read-only
T32A Run Register B
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUNB : RUNB
bits : 0 - 0 (1 bit)
access : read-write
SFTSTAB : SFTSTAB
bits : 1 - 1 (1 bit)
access : write-only
SFTSTPB : SFTSTPB
bits : 2 - 2 (1 bit)
access : write-only
RUNFLGB : RUNFLGB
bits : 4 - 4 (1 bit)
access : read-only
T32A Control Register B
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTB : STARTB
bits : 0 - 2 (3 bit)
access : read-write
STOPB : STOPB
bits : 4 - 6 (3 bit)
access : read-write
RELDB : RELDB
bits : 8 - 10 (3 bit)
access : read-write
UPDNB : UPDNB
bits : 16 - 17 (2 bit)
access : read-write
WBFB : WBFB
bits : 20 - 20 (1 bit)
access : read-write
CLKB : CLKB
bits : 24 - 26 (3 bit)
access : read-write
PRSCLB : PRSCLB
bits : 28 - 30 (3 bit)
access : read-write
T32A Capture Control Register B
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPMB0 : CAPMB0
bits : 0 - 2 (3 bit)
access : read-write
CAPMB1 : CAPMB1
bits : 4 - 6 (3 bit)
access : read-write
T32A Output Control Register B0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OCRB : OCRB
bits : 0 - 1 (2 bit)
access : write-only
T32A Output Control Register B1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCRCMPB0 : OCRCMPB0
bits : 0 - 1 (2 bit)
access : read-write
OCRCMPB1 : OCRCMPB1
bits : 2 - 3 (2 bit)
access : read-write
OCRCAPB0 : OCRCAPB0
bits : 4 - 5 (2 bit)
access : read-write
OCRCAPB1 : OCRCAPB1
bits : 6 - 7 (2 bit)
access : read-write
T32A Status Register B
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTB0 : INTB0
bits : 0 - 0 (1 bit)
access : read-write
INTB1 : INTB1
bits : 1 - 1 (1 bit)
access : read-write
INTOFB : INTOFB
bits : 2 - 2 (1 bit)
access : read-write
INTUFB : INTUFB
bits : 3 - 3 (1 bit)
access : read-write
T32A Interrupt Mask Register B
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMB0 : IMB0
bits : 0 - 0 (1 bit)
access : read-write
IMB1 : IMB1
bits : 1 - 1 (1 bit)
access : read-write
IMOFB : IMOFB
bits : 2 - 2 (1 bit)
access : read-write
IMUFB : IMUFB
bits : 3 - 3 (1 bit)
access : read-write
T32A Counter Capture Register B
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMRB : TMRB
bits : 0 - 15 (16 bit)
access : read-only
T32A Reload Register B
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELDB : RELDB
bits : 0 - 15 (16 bit)
access : read-write
T32A Timer Register B0
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGB0 : RGB0
bits : 0 - 15 (16 bit)
access : read-write
T32A Timer Register B1
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGB1 : RGB1
bits : 0 - 15 (16 bit)
access : read-write
T32A Capture Register B0
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPB0 : CAPB0
bits : 0 - 15 (16 bit)
access : read-only
T32A Capture Register B1
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPB1 : CAPB1
bits : 0 - 15 (16 bit)
access : read-only
T32A DMA Request Enable Register B
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAENB0 : DMAENB0
bits : 0 - 0 (1 bit)
access : read-write
DMAENB1 : DMAENB1
bits : 1 - 1 (1 bit)
access : read-write
DMAENB2 : DMAENB2
bits : 2 - 2 (1 bit)
access : read-write
T32A Compare Register B0
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRGB0 : CRGB0
bits : 0 - 15 (16 bit)
access : read-only
T32A Compare Register B1
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRGB1 : CRGB1
bits : 0 - 15 (16 bit)
access : read-only
T32A Run Register C
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUNC : RUNC
bits : 0 - 0 (1 bit)
access : read-write
SFTSTAC : SFTSTAC
bits : 1 - 1 (1 bit)
access : write-only
SFTSTPC : SFTSTPC
bits : 2 - 2 (1 bit)
access : write-only
RUNFLGC : RUNFLGC
bits : 4 - 4 (1 bit)
access : read-only
T32A Control Register C
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTC : STARTC
bits : 0 - 2 (3 bit)
access : read-write
STOPC : STOPC
bits : 4 - 6 (3 bit)
access : read-write
RELDC : RELDC
bits : 8 - 10 (3 bit)
access : read-write
UPDNC : UPDNC
bits : 16 - 17 (2 bit)
access : read-write
WBFC : WBFC
bits : 20 - 20 (1 bit)
access : read-write
CLKC : CLKC
bits : 24 - 26 (3 bit)
access : read-write
PRSCLC : PRSCLC
bits : 28 - 30 (3 bit)
access : read-write
T32A Capture Control Register C
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPMC0 : CAPMC0
bits : 0 - 2 (3 bit)
access : read-write
CAPMC1 : CAPMC1
bits : 4 - 6 (3 bit)
access : read-write
T32A Output Control Register C0
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OCRC : OCRC
bits : 0 - 1 (2 bit)
access : write-only
T32A Output Control Register C1
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCRCMPC0 : OCRCMPC0
bits : 0 - 1 (2 bit)
access : read-write
OCRCMPC1 : OCRCMPC1
bits : 2 - 3 (2 bit)
access : read-write
OCRCAPC0 : OCRCAPC0
bits : 4 - 5 (2 bit)
access : read-write
OCRCAPC1 : OCRCAPC1
bits : 6 - 7 (2 bit)
access : read-write
T32A Status Register C
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTC0 : INTC0
bits : 0 - 0 (1 bit)
access : read-write
INTC1 : INTC1
bits : 1 - 1 (1 bit)
access : read-write
INTOFC : INTOFC
bits : 2 - 2 (1 bit)
access : read-write
INTUFC : INTUFC
bits : 3 - 3 (1 bit)
access : read-write
INTSTERR : INTSTERR
bits : 4 - 4 (1 bit)
access : read-write
T32A Interrupt Mask Register C
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMC0 : IMC0
bits : 0 - 0 (1 bit)
access : read-write
IMC1 : IMC1
bits : 1 - 1 (1 bit)
access : read-write
IMOFC : IMOFC
bits : 2 - 2 (1 bit)
access : read-write
IMUFC : IMUFC
bits : 3 - 3 (1 bit)
access : read-write
IMSTERR : IMSTERR
bits : 4 - 4 (1 bit)
access : read-write
T32A Counter Capture Register C
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMRC : TMRC
bits : 0 - 31 (32 bit)
access : read-only
T32A Reload Register C
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELDC : RELDC
bits : 0 - 31 (32 bit)
access : read-write
T32A Timer Register C0
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGC0 : RGC0
bits : 0 - 31 (32 bit)
access : read-write
T32A Timer Register C1
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGC1 : RGC1
bits : 0 - 31 (32 bit)
access : read-write
T32A Capture Register C0
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPC0 : CAPC0
bits : 0 - 31 (32 bit)
access : read-only
T32A Capture Register C1
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPC1 : CAPC1
bits : 0 - 31 (32 bit)
access : read-only
T32A DMA Request Enable Register C
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAENC0 : DMAENC0
bits : 0 - 0 (1 bit)
access : read-write
DMAENC1 : DMAENC1
bits : 1 - 1 (1 bit)
access : read-write
DMAENC2 : DMAENC2
bits : 2 - 2 (1 bit)
access : read-write
T32A Pulse Count Control Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMODE : PMODE
bits : 0 - 0 (1 bit)
access : read-write
PDIR : PDIR
bits : 1 - 1 (1 bit)
access : read-write
NF : NF
bits : 4 - 5 (2 bit)
access : read-write
PUP : PUP
bits : 8 - 10 (3 bit)
access : read-write
PDN : PDN
bits : 12 - 14 (3 bit)
access : read-write
T32A Compare Register C0
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRGC0 : CRGC0
bits : 0 - 31 (32 bit)
access : read-only
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