\n

CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x3C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x48 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x54 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x5C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x64 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x68 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x6C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x70 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x74 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x78 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x7C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x84 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x88 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x94 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x98 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x9C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0xA0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xA4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0xA8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xAC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xB4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0xB8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

MC

TRS

TRR

TA

AA

RMP

RML

LAM

GAM

MCR

GSR

BCR1

BCR2

GIF

GIM

MD

MBTIF

MBRIF

MBIM

CDR

RFP

CEC

TSP

TSC


MC

CAN Mailbox Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MC MC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 MC8 MC9 MC10 MC11 MC12 MC13 MC14 MC15 MC16 MC17 MC18 MC19 MC20 MC21 MC22 MC23 MC24 MC25 MC26 MC27 MC28 MC29 MC30 MC31

MC0 : MC0
bits : 0 - 0 (1 bit)
access : read-write

MC1 : MC1
bits : 1 - 1 (1 bit)
access : read-write

MC2 : MC2
bits : 2 - 2 (1 bit)
access : read-write

MC3 : MC3
bits : 3 - 3 (1 bit)
access : read-write

MC4 : MC4
bits : 4 - 4 (1 bit)
access : read-write

MC5 : MC5
bits : 5 - 5 (1 bit)
access : read-write

MC6 : MC6
bits : 6 - 6 (1 bit)
access : read-write

MC7 : MC7
bits : 7 - 7 (1 bit)
access : read-write

MC8 : MC8
bits : 8 - 8 (1 bit)
access : read-write

MC9 : MC9
bits : 9 - 9 (1 bit)
access : read-write

MC10 : MC10
bits : 10 - 10 (1 bit)
access : read-write

MC11 : MC11
bits : 11 - 11 (1 bit)
access : read-write

MC12 : MC12
bits : 12 - 12 (1 bit)
access : read-write

MC13 : MC13
bits : 13 - 13 (1 bit)
access : read-write

MC14 : MC14
bits : 14 - 14 (1 bit)
access : read-write

MC15 : MC15
bits : 15 - 15 (1 bit)
access : read-write

MC16 : MC16
bits : 16 - 16 (1 bit)
access : read-write

MC17 : MC17
bits : 17 - 17 (1 bit)
access : read-write

MC18 : MC18
bits : 18 - 18 (1 bit)
access : read-write

MC19 : MC19
bits : 19 - 19 (1 bit)
access : read-write

MC20 : MC20
bits : 20 - 20 (1 bit)
access : read-write

MC21 : MC21
bits : 21 - 21 (1 bit)
access : read-write

MC22 : MC22
bits : 22 - 22 (1 bit)
access : read-write

MC23 : MC23
bits : 23 - 23 (1 bit)
access : read-write

MC24 : MC24
bits : 24 - 24 (1 bit)
access : read-write

MC25 : MC25
bits : 25 - 25 (1 bit)
access : read-write

MC26 : MC26
bits : 26 - 26 (1 bit)
access : read-write

MC27 : MC27
bits : 27 - 27 (1 bit)
access : read-write

MC28 : MC28
bits : 28 - 28 (1 bit)
access : read-write

MC29 : MC29
bits : 29 - 29 (1 bit)
access : read-write

MC30 : MC30
bits : 30 - 30 (1 bit)
access : read-write

MC31 : MC31
bits : 31 - 31 (1 bit)
access : read-write


TRS

CAN Transmit Request Set Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRS TRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRS0 TRS1 TRS2 TRS3 TRS4 TRS5 TRS6 TRS7 TRS8 TRS9 TRS10 TRS11 TRS12 TRS13 TRS14 TRS15 TRS16 TRS17 TRS18 TRS19 TRS20 TRS21 TRS22 TRS23 TRS24 TRS25 TRS26 TRS27 TRS28 TRS29 TRS30

TRS0 : TRS0
bits : 0 - 0 (1 bit)
access : read-write

TRS1 : TRS1
bits : 1 - 1 (1 bit)
access : read-write

TRS2 : TRS2
bits : 2 - 2 (1 bit)
access : read-write

TRS3 : TRS3
bits : 3 - 3 (1 bit)
access : read-write

TRS4 : TRS4
bits : 4 - 4 (1 bit)
access : read-write

TRS5 : TRS5
bits : 5 - 5 (1 bit)
access : read-write

TRS6 : TRS6
bits : 6 - 6 (1 bit)
access : read-write

TRS7 : TRS7
bits : 7 - 7 (1 bit)
access : read-write

TRS8 : TRS8
bits : 8 - 8 (1 bit)
access : read-write

TRS9 : TRS9
bits : 9 - 9 (1 bit)
access : read-write

TRS10 : TRS10
bits : 10 - 10 (1 bit)
access : read-write

TRS11 : TRS11
bits : 11 - 11 (1 bit)
access : read-write

TRS12 : TRS12
bits : 12 - 12 (1 bit)
access : read-write

TRS13 : TRS13
bits : 13 - 13 (1 bit)
access : read-write

TRS14 : TRS14
bits : 14 - 14 (1 bit)
access : read-write

TRS15 : TRS15
bits : 15 - 15 (1 bit)
access : read-write

TRS16 : TRS16
bits : 16 - 16 (1 bit)
access : read-write

TRS17 : TRS17
bits : 17 - 17 (1 bit)
access : read-write

TRS18 : TRS18
bits : 18 - 18 (1 bit)
access : read-write

TRS19 : TRS19
bits : 19 - 19 (1 bit)
access : read-write

TRS20 : TRS20
bits : 20 - 20 (1 bit)
access : read-write

TRS21 : TRS21
bits : 21 - 21 (1 bit)
access : read-write

TRS22 : TRS22
bits : 22 - 22 (1 bit)
access : read-write

TRS23 : TRS23
bits : 23 - 23 (1 bit)
access : read-write

TRS24 : TRS24
bits : 24 - 24 (1 bit)
access : read-write

TRS25 : TRS25
bits : 25 - 25 (1 bit)
access : read-write

TRS26 : TRS26
bits : 26 - 26 (1 bit)
access : read-write

TRS27 : TRS27
bits : 27 - 27 (1 bit)
access : read-write

TRS28 : TRS28
bits : 28 - 28 (1 bit)
access : read-write

TRS29 : TRS29
bits : 29 - 29 (1 bit)
access : read-write

TRS30 : TRS30
bits : 30 - 30 (1 bit)
access : read-write


TRR

CAN Transmit Request Reset Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRR TRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRR0 TRR1 TRR2 TRR3 TRR4 TRR5 TRR6 TRR7 TRR8 TRR9 TRR10 TRR11 TRR12 TRR13 TRR14 TRR15 TRR16 TRR17 TRR18 TRR19 TRR20 TRR21 TRR22 TRR23 TRR24 TRR25 TRR26 TRR27 TRR28 TRR29 TRR30

TRR0 : TRR0
bits : 0 - 0 (1 bit)
access : read-write

TRR1 : TRR1
bits : 1 - 1 (1 bit)
access : read-write

TRR2 : TRR2
bits : 2 - 2 (1 bit)
access : read-write

TRR3 : TRR3
bits : 3 - 3 (1 bit)
access : read-write

TRR4 : TRR4
bits : 4 - 4 (1 bit)
access : read-write

TRR5 : TRR5
bits : 5 - 5 (1 bit)
access : read-write

TRR6 : TRR6
bits : 6 - 6 (1 bit)
access : read-write

TRR7 : TRR7
bits : 7 - 7 (1 bit)
access : read-write

TRR8 : TRR8
bits : 8 - 8 (1 bit)
access : read-write

TRR9 : TRR9
bits : 9 - 9 (1 bit)
access : read-write

TRR10 : TRR10
bits : 10 - 10 (1 bit)
access : read-write

TRR11 : TRR11
bits : 11 - 11 (1 bit)
access : read-write

TRR12 : TRR12
bits : 12 - 12 (1 bit)
access : read-write

TRR13 : TRR13
bits : 13 - 13 (1 bit)
access : read-write

TRR14 : TRR14
bits : 14 - 14 (1 bit)
access : read-write

TRR15 : TRR15
bits : 15 - 15 (1 bit)
access : read-write

TRR16 : TRR16
bits : 16 - 16 (1 bit)
access : read-write

TRR17 : TRR17
bits : 17 - 17 (1 bit)
access : read-write

TRR18 : TRR18
bits : 18 - 18 (1 bit)
access : read-write

TRR19 : TRR19
bits : 19 - 19 (1 bit)
access : read-write

TRR20 : TRR20
bits : 20 - 20 (1 bit)
access : read-write

TRR21 : TRR21
bits : 21 - 21 (1 bit)
access : read-write

TRR22 : TRR22
bits : 22 - 22 (1 bit)
access : read-write

TRR23 : TRR23
bits : 23 - 23 (1 bit)
access : read-write

TRR24 : TRR24
bits : 24 - 24 (1 bit)
access : read-write

TRR25 : TRR25
bits : 25 - 25 (1 bit)
access : read-write

TRR26 : TRR26
bits : 26 - 26 (1 bit)
access : read-write

TRR27 : TRR27
bits : 27 - 27 (1 bit)
access : read-write

TRR28 : TRR28
bits : 28 - 28 (1 bit)
access : read-write

TRR29 : TRR29
bits : 29 - 29 (1 bit)
access : read-write

TRR30 : TRR30
bits : 30 - 30 (1 bit)
access : read-write


TA

CAN Transmission Acknowledge Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TA TA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 TA10 TA11 TA12 TA13 TA14 TA15 TA16 TA17 TA18 TA19 TA20 TA21 TA22 TA23 TA24 TA25 TA26 TA27 TA28 TA29 TA30

TA0 : TA0
bits : 0 - 0 (1 bit)
access : read-write

TA1 : TA1
bits : 1 - 1 (1 bit)
access : read-write

TA2 : TA2
bits : 2 - 2 (1 bit)
access : read-write

TA3 : TA3
bits : 3 - 3 (1 bit)
access : read-write

TA4 : TA4
bits : 4 - 4 (1 bit)
access : read-write

TA5 : TA5
bits : 5 - 5 (1 bit)
access : read-write

TA6 : TA6
bits : 6 - 6 (1 bit)
access : read-write

TA7 : TA7
bits : 7 - 7 (1 bit)
access : read-write

TA8 : TA8
bits : 8 - 8 (1 bit)
access : read-write

TA9 : TA9
bits : 9 - 9 (1 bit)
access : read-write

TA10 : TA10
bits : 10 - 10 (1 bit)
access : read-write

TA11 : TA11
bits : 11 - 11 (1 bit)
access : read-write

TA12 : TA12
bits : 12 - 12 (1 bit)
access : read-write

TA13 : TA13
bits : 13 - 13 (1 bit)
access : read-write

TA14 : TA14
bits : 14 - 14 (1 bit)
access : read-write

TA15 : TA15
bits : 15 - 15 (1 bit)
access : read-write

TA16 : TA16
bits : 16 - 16 (1 bit)
access : read-write

TA17 : TA17
bits : 17 - 17 (1 bit)
access : read-write

TA18 : TA18
bits : 18 - 18 (1 bit)
access : read-write

TA19 : TA19
bits : 19 - 19 (1 bit)
access : read-write

TA20 : TA20
bits : 20 - 20 (1 bit)
access : read-write

TA21 : TA21
bits : 21 - 21 (1 bit)
access : read-write

TA22 : TA22
bits : 22 - 22 (1 bit)
access : read-write

TA23 : TA23
bits : 23 - 23 (1 bit)
access : read-write

TA24 : TA24
bits : 24 - 24 (1 bit)
access : read-write

TA25 : TA25
bits : 25 - 25 (1 bit)
access : read-write

TA26 : TA26
bits : 26 - 26 (1 bit)
access : read-write

TA27 : TA27
bits : 27 - 27 (1 bit)
access : read-write

TA28 : TA28
bits : 28 - 28 (1 bit)
access : read-write

TA29 : TA29
bits : 29 - 29 (1 bit)
access : read-write

TA30 : TA30
bits : 30 - 30 (1 bit)
access : read-write


AA

CAN Abort Acknowledge Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AA AA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30

AA0 : AA0
bits : 0 - 0 (1 bit)
access : read-write

AA1 : AA1
bits : 1 - 1 (1 bit)
access : read-write

AA2 : AA2
bits : 2 - 2 (1 bit)
access : read-write

AA3 : AA3
bits : 3 - 3 (1 bit)
access : read-write

AA4 : AA4
bits : 4 - 4 (1 bit)
access : read-write

AA5 : AA5
bits : 5 - 5 (1 bit)
access : read-write

AA6 : AA6
bits : 6 - 6 (1 bit)
access : read-write

AA7 : AA7
bits : 7 - 7 (1 bit)
access : read-write

AA8 : AA8
bits : 8 - 8 (1 bit)
access : read-write

AA9 : AA9
bits : 9 - 9 (1 bit)
access : read-write

AA10 : AA10
bits : 10 - 10 (1 bit)
access : read-write

AA11 : AA11
bits : 11 - 11 (1 bit)
access : read-write

AA12 : AA12
bits : 12 - 12 (1 bit)
access : read-write

AA13 : AA13
bits : 13 - 13 (1 bit)
access : read-write

AA14 : AA14
bits : 14 - 14 (1 bit)
access : read-write

AA15 : AA15
bits : 15 - 15 (1 bit)
access : read-write

AA16 : AA16
bits : 16 - 16 (1 bit)
access : read-write

AA17 : AA17
bits : 17 - 17 (1 bit)
access : read-write

AA18 : AA18
bits : 18 - 18 (1 bit)
access : read-write

AA19 : AA19
bits : 19 - 19 (1 bit)
access : read-write

AA20 : AA20
bits : 20 - 20 (1 bit)
access : read-write

AA21 : AA21
bits : 21 - 21 (1 bit)
access : read-write

AA22 : AA22
bits : 22 - 22 (1 bit)
access : read-write

AA23 : AA23
bits : 23 - 23 (1 bit)
access : read-write

AA24 : AA24
bits : 24 - 24 (1 bit)
access : read-write

AA25 : AA25
bits : 25 - 25 (1 bit)
access : read-write

AA26 : AA26
bits : 26 - 26 (1 bit)
access : read-write

AA27 : AA27
bits : 27 - 27 (1 bit)
access : read-write

AA28 : AA28
bits : 28 - 28 (1 bit)
access : read-write

AA29 : AA29
bits : 29 - 29 (1 bit)
access : read-write

AA30 : AA30
bits : 30 - 30 (1 bit)
access : read-write


RMP

CAN Receive Message Pending Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RMP RMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMP0 RMP1 RMP2 RMP3 RMP4 RMP5 RMP6 RMP7 RMP8 RMP9 RMP10 RMP11 RMP12 RMP13 RMP14 RMP15 RMP16 RMP17 RMP18 RMP19 RMP20 RMP21 RMP22 RMP23 RMP24 RMP25 RMP26 RMP27 RMP28 RMP29 RMP30 RMP31

RMP0 : RMP0
bits : 0 - 0 (1 bit)
access : read-write

RMP1 : RMP1
bits : 1 - 1 (1 bit)
access : read-write

RMP2 : RMP2
bits : 2 - 2 (1 bit)
access : read-write

RMP3 : RMP3
bits : 3 - 3 (1 bit)
access : read-write

RMP4 : RMP4
bits : 4 - 4 (1 bit)
access : read-write

RMP5 : RMP5
bits : 5 - 5 (1 bit)
access : read-write

RMP6 : RMP6
bits : 6 - 6 (1 bit)
access : read-write

RMP7 : RMP7
bits : 7 - 7 (1 bit)
access : read-write

RMP8 : RMP8
bits : 8 - 8 (1 bit)
access : read-write

RMP9 : RMP9
bits : 9 - 9 (1 bit)
access : read-write

RMP10 : RMP10
bits : 10 - 10 (1 bit)
access : read-write

RMP11 : RMP11
bits : 11 - 11 (1 bit)
access : read-write

RMP12 : RMP12
bits : 12 - 12 (1 bit)
access : read-write

RMP13 : RMP13
bits : 13 - 13 (1 bit)
access : read-write

RMP14 : RMP14
bits : 14 - 14 (1 bit)
access : read-write

RMP15 : RMP15
bits : 15 - 15 (1 bit)
access : read-write

RMP16 : RMP16
bits : 16 - 16 (1 bit)
access : read-write

RMP17 : RMP17
bits : 17 - 17 (1 bit)
access : read-write

RMP18 : RMP18
bits : 18 - 18 (1 bit)
access : read-write

RMP19 : RMP19
bits : 19 - 19 (1 bit)
access : read-write

RMP20 : RMP20
bits : 20 - 20 (1 bit)
access : read-write

RMP21 : RMP21
bits : 21 - 21 (1 bit)
access : read-write

RMP22 : RMP22
bits : 22 - 22 (1 bit)
access : read-write

RMP23 : RMP23
bits : 23 - 23 (1 bit)
access : read-write

RMP24 : RMP24
bits : 24 - 24 (1 bit)
access : read-write

RMP25 : RMP25
bits : 25 - 25 (1 bit)
access : read-write

RMP26 : RMP26
bits : 26 - 26 (1 bit)
access : read-write

RMP27 : RMP27
bits : 27 - 27 (1 bit)
access : read-write

RMP28 : RMP28
bits : 28 - 28 (1 bit)
access : read-write

RMP29 : RMP29
bits : 29 - 29 (1 bit)
access : read-write

RMP30 : RMP30
bits : 30 - 30 (1 bit)
access : read-write

RMP31 : RMP31
bits : 31 - 31 (1 bit)
access : read-write


RML

CAN Receive Message Lost Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RML RML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RML0 RML1 RML2 RML3 RML4 RML5 RML6 RML7 RML8 RML9 RML10 RML11 RML12 RML13 RML14 RML15 RML16 RML17 RML18 RML19 RML20 RML21 RML22 RML23 RML24 RML25 RML26 RML27 RML28 RML29 RML30 RML31

RML0 : RML0
bits : 0 - 0 (1 bit)
access : read-write

RML1 : RML1
bits : 1 - 1 (1 bit)
access : read-write

RML2 : RML2
bits : 2 - 2 (1 bit)
access : read-write

RML3 : RML3
bits : 3 - 3 (1 bit)
access : read-write

RML4 : RML4
bits : 4 - 4 (1 bit)
access : read-write

RML5 : RML5
bits : 5 - 5 (1 bit)
access : read-write

RML6 : RML6
bits : 6 - 6 (1 bit)
access : read-write

RML7 : RML7
bits : 7 - 7 (1 bit)
access : read-write

RML8 : RML8
bits : 8 - 8 (1 bit)
access : read-write

RML9 : RML9
bits : 9 - 9 (1 bit)
access : read-write

RML10 : RML10
bits : 10 - 10 (1 bit)
access : read-write

RML11 : RML11
bits : 11 - 11 (1 bit)
access : read-write

RML12 : RML12
bits : 12 - 12 (1 bit)
access : read-write

RML13 : RML13
bits : 13 - 13 (1 bit)
access : read-write

RML14 : RML14
bits : 14 - 14 (1 bit)
access : read-write

RML15 : RML15
bits : 15 - 15 (1 bit)
access : read-write

RML16 : RML16
bits : 16 - 16 (1 bit)
access : read-write

RML17 : RML17
bits : 17 - 17 (1 bit)
access : read-write

RML18 : RML18
bits : 18 - 18 (1 bit)
access : read-write

RML19 : RML19
bits : 19 - 19 (1 bit)
access : read-write

RML20 : RML20
bits : 20 - 20 (1 bit)
access : read-write

RML21 : RML21
bits : 21 - 21 (1 bit)
access : read-write

RML22 : RML22
bits : 22 - 22 (1 bit)
access : read-write

RML23 : RML23
bits : 23 - 23 (1 bit)
access : read-write

RML24 : RML24
bits : 24 - 24 (1 bit)
access : read-write

RML25 : RML25
bits : 25 - 25 (1 bit)
access : read-write

RML26 : RML26
bits : 26 - 26 (1 bit)
access : read-write

RML27 : RML27
bits : 27 - 27 (1 bit)
access : read-write

RML28 : RML28
bits : 28 - 28 (1 bit)
access : read-write

RML29 : RML29
bits : 29 - 29 (1 bit)
access : read-write

RML30 : RML30
bits : 30 - 30 (1 bit)
access : read-write

RML31 : RML31
bits : 31 - 31 (1 bit)
access : read-write


LAM

CAN Local Acceptance Mask Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LAM LAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAM LAMI

LAM : LAM
bits : 0 - 28 (29 bit)
access : read-write

LAMI : LAMI
bits : 31 - 31 (1 bit)
access : read-write


GAM

CAN Global Acceptance Mask Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAM GAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAM GAMI

GAM : GAM
bits : 0 - 28 (29 bit)
access : read-write

GAMI : GAMI
bits : 31 - 31 (1 bit)
access : read-write


MCR

CAN Master Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRES TSCC MTOS WUBA SMR CCR TSTERR TSTLB SUR

SRES : SRES
bits : 0 - 0 (1 bit)
access : read-write

TSCC : TSCC
bits : 1 - 1 (1 bit)
access : read-write

MTOS : MTOS
bits : 3 - 3 (1 bit)
access : read-write

WUBA : WUBA
bits : 4 - 4 (1 bit)
access : read-write

SMR : SMR
bits : 6 - 6 (1 bit)
access : read-write

CCR : CCR
bits : 7 - 7 (1 bit)
access : read-write

TSTERR : TSTERR
bits : 8 - 8 (1 bit)
access : read-write

TSTLB : TSTLB
bits : 9 - 9 (1 bit)
access : read-write

SUR : SUR
bits : 11 - 11 (1 bit)
access : read-write


GSR

CAN Global Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GSR GSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EW EP BO TSO SMA CCE SUA TM RM MIS

EW : EW
bits : 0 - 0 (1 bit)
access : read-only

EP : EP
bits : 1 - 1 (1 bit)
access : read-only

BO : BO
bits : 2 - 2 (1 bit)
access : read-only

TSO : TSO
bits : 3 - 3 (1 bit)
access : read-only

SMA : SMA
bits : 6 - 6 (1 bit)
access : read-only

CCE : CCE
bits : 7 - 7 (1 bit)
access : read-only

SUA : SUA
bits : 8 - 8 (1 bit)
access : read-only

TM : TM
bits : 10 - 10 (1 bit)
access : read-only

RM : RM
bits : 11 - 11 (1 bit)
access : read-only

MIS : MIS
bits : 12 - 16 (5 bit)
access : read-only


BCR1

CAN Bit Configuration Register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR1 BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRP

BRP : BRP
bits : 0 - 9 (10 bit)
access : read-write


BCR2

CAN Bit Configuration Register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR2 BCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEG1 TSEG2 SAM SJW

TSEG1 : TSEG1
bits : 0 - 3 (4 bit)
access : read-write

TSEG2 : TSEG2
bits : 4 - 6 (3 bit)
access : read-write

SAM : SAM
bits : 7 - 7 (1 bit)
access : read-write

SJW : SJW
bits : 8 - 9 (2 bit)
access : read-write


GIF

CAN Global Interrupt Flag Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GIF GIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLIF EPIF BOIF TSOIF TRMABF RMLIF WUIF RFPF

WLIF : WLIF
bits : 0 - 0 (1 bit)
access : read-write

EPIF : EPIF
bits : 1 - 1 (1 bit)
access : read-write

BOIF : BOIF
bits : 2 - 2 (1 bit)
access : read-write

TSOIF : TSOIF
bits : 3 - 3 (1 bit)
access : read-write

TRMABF : TRMABF
bits : 4 - 4 (1 bit)
access : read-write

RMLIF : RMLIF
bits : 5 - 5 (1 bit)
access : read-write

WUIF : WUIF
bits : 6 - 6 (1 bit)
access : read-write

RFPF : RFPF
bits : 7 - 7 (1 bit)
access : read-write


GIM

CAN Global Interrupt Mask Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GIM GIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLIM EPIM BOIM TSOIM TRMABF RMLIM WUIM RFPM

WLIM : WLIM
bits : 0 - 0 (1 bit)
access : read-write

EPIM : EPIM
bits : 1 - 1 (1 bit)
access : read-write

BOIM : BOIM
bits : 2 - 2 (1 bit)
access : read-write

TSOIM : TSOIM
bits : 3 - 3 (1 bit)
access : read-write

TRMABF : TRMABF
bits : 4 - 4 (1 bit)
access : read-write

RMLIM : RMLIM
bits : 5 - 5 (1 bit)
access : read-write

WUIM : WUIM
bits : 6 - 6 (1 bit)
access : read-write

RFPM : RFPM
bits : 7 - 7 (1 bit)
access : read-write


MD

CAN Mailbox Direction Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MD MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

MD0 : MD0
bits : 0 - 0 (1 bit)
access : read-write

MD1 : MD1
bits : 1 - 1 (1 bit)
access : read-write

MD2 : MD2
bits : 2 - 2 (1 bit)
access : read-write

MD3 : MD3
bits : 3 - 3 (1 bit)
access : read-write

MD4 : MD4
bits : 4 - 4 (1 bit)
access : read-write

MD5 : MD5
bits : 5 - 5 (1 bit)
access : read-write

MD6 : MD6
bits : 6 - 6 (1 bit)
access : read-write

MD7 : MD7
bits : 7 - 7 (1 bit)
access : read-write

MD8 : MD8
bits : 8 - 8 (1 bit)
access : read-write

MD9 : MD9
bits : 9 - 9 (1 bit)
access : read-write

MD10 : MD10
bits : 10 - 10 (1 bit)
access : read-write

MD11 : MD11
bits : 11 - 11 (1 bit)
access : read-write

MD12 : MD12
bits : 12 - 12 (1 bit)
access : read-write

MD13 : MD13
bits : 13 - 13 (1 bit)
access : read-write

MD14 : MD14
bits : 14 - 14 (1 bit)
access : read-write

MD15 : MD15
bits : 15 - 15 (1 bit)
access : read-write

MD16 : MD16
bits : 16 - 16 (1 bit)
access : read-write

MD17 : MD17
bits : 17 - 17 (1 bit)
access : read-write

MD18 : MD18
bits : 18 - 18 (1 bit)
access : read-write

MD19 : MD19
bits : 19 - 19 (1 bit)
access : read-write

MD20 : MD20
bits : 20 - 20 (1 bit)
access : read-write

MD21 : MD21
bits : 21 - 21 (1 bit)
access : read-write

MD22 : MD22
bits : 22 - 22 (1 bit)
access : read-write

MD23 : MD23
bits : 23 - 23 (1 bit)
access : read-write

MD24 : MD24
bits : 24 - 24 (1 bit)
access : read-write

MD25 : MD25
bits : 25 - 25 (1 bit)
access : read-write

MD26 : MD26
bits : 26 - 26 (1 bit)
access : read-write

MD27 : MD27
bits : 27 - 27 (1 bit)
access : read-write

MD28 : MD28
bits : 28 - 28 (1 bit)
access : read-write

MD29 : MD29
bits : 29 - 29 (1 bit)
access : read-write

MD30 : MD30
bits : 30 - 30 (1 bit)
access : read-write

MD31 : MD31
bits : 31 - 31 (1 bit)
access : read-only


MBTIF

CAN Mailbox Transmit Interrupt Flag Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBTIF MBTIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBTIF0 MBTIF1 MBTIF2 MBTIF3 MBTIF4 MBTIF5 MBTIF6 MBTIF7 MBTIF8 MBTIF9 MBTIF10 MBTIF11 MBTIF12 MBTIF13 MBTIF14 MBTIF15 MBTIF16 MBTIF17 MBTIF18 MBTIF19 MBTIF20 MBTIF21 MBTIF22 MBTIF23 MBTIF24 MBTIF25 MBTIF26 MBTIF27 MBTIF28 MBTIF29 MBTIF30

MBTIF0 : MBTIF0
bits : 0 - 0 (1 bit)
access : read-write

MBTIF1 : MBTIF1
bits : 1 - 1 (1 bit)
access : read-write

MBTIF2 : MBTIF2
bits : 2 - 2 (1 bit)
access : read-write

MBTIF3 : MBTIF3
bits : 3 - 3 (1 bit)
access : read-write

MBTIF4 : MBTIF4
bits : 4 - 4 (1 bit)
access : read-write

MBTIF5 : MBTIF5
bits : 5 - 5 (1 bit)
access : read-write

MBTIF6 : MBTIF6
bits : 6 - 6 (1 bit)
access : read-write

MBTIF7 : MBTIF7
bits : 7 - 7 (1 bit)
access : read-write

MBTIF8 : MBTIF8
bits : 8 - 8 (1 bit)
access : read-write

MBTIF9 : MBTIF9
bits : 9 - 9 (1 bit)
access : read-write

MBTIF10 : MBTIF10
bits : 10 - 10 (1 bit)
access : read-write

MBTIF11 : MBTIF11
bits : 11 - 11 (1 bit)
access : read-write

MBTIF12 : MBTIF12
bits : 12 - 12 (1 bit)
access : read-write

MBTIF13 : MBTIF13
bits : 13 - 13 (1 bit)
access : read-write

MBTIF14 : MBTIF14
bits : 14 - 14 (1 bit)
access : read-write

MBTIF15 : MBTIF15
bits : 15 - 15 (1 bit)
access : read-write

MBTIF16 : MBTIF16
bits : 16 - 16 (1 bit)
access : read-write

MBTIF17 : MBTIF17
bits : 17 - 17 (1 bit)
access : read-write

MBTIF18 : MBTIF18
bits : 18 - 18 (1 bit)
access : read-write

MBTIF19 : MBTIF19
bits : 19 - 19 (1 bit)
access : read-write

MBTIF20 : MBTIF20
bits : 20 - 20 (1 bit)
access : read-write

MBTIF21 : MBTIF21
bits : 21 - 21 (1 bit)
access : read-write

MBTIF22 : MBTIF22
bits : 22 - 22 (1 bit)
access : read-write

MBTIF23 : MBTIF23
bits : 23 - 23 (1 bit)
access : read-write

MBTIF24 : MBTIF24
bits : 24 - 24 (1 bit)
access : read-write

MBTIF25 : MBTIF25
bits : 25 - 25 (1 bit)
access : read-write

MBTIF26 : MBTIF26
bits : 26 - 26 (1 bit)
access : read-write

MBTIF27 : MBTIF27
bits : 27 - 27 (1 bit)
access : read-write

MBTIF28 : MBTIF28
bits : 28 - 28 (1 bit)
access : read-write

MBTIF29 : MBTIF29
bits : 29 - 29 (1 bit)
access : read-write

MBTIF30 : MBTIF30
bits : 30 - 30 (1 bit)
access : read-write


MBRIF

CAN Mailbox Receive Interrupt Flag Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBRIF MBRIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBRIF0 MBRIF1 MBRIF2 MBRIF3 MBRIF4 MBRIF5 MBRIF6 MBRIF7 MBRIF8 MBRIF9 MBRIF10 MBRIF11 MBRIF12 MBRIF13 MBRIF14 MBRIF15 MBRIF16 MBRIF17 MBRIF18 MBRIF19 MBRIF20 MBRIF21 MBRIF22 MBRIF23 MBRIF24 MBRIF25 MBRIF26 MBRIF27 MBRIF28 MBRIF29 MBRIF30 MBRIF31

MBRIF0 : MBRIF0
bits : 0 - 0 (1 bit)
access : read-write

MBRIF1 : MBRIF1
bits : 1 - 1 (1 bit)
access : read-write

MBRIF2 : MBRIF2
bits : 2 - 2 (1 bit)
access : read-write

MBRIF3 : MBRIF3
bits : 3 - 3 (1 bit)
access : read-write

MBRIF4 : MBRIF4
bits : 4 - 4 (1 bit)
access : read-write

MBRIF5 : MBRIF5
bits : 5 - 5 (1 bit)
access : read-write

MBRIF6 : MBRIF6
bits : 6 - 6 (1 bit)
access : read-write

MBRIF7 : MBRIF7
bits : 7 - 7 (1 bit)
access : read-write

MBRIF8 : MBRIF8
bits : 8 - 8 (1 bit)
access : read-write

MBRIF9 : MBRIF9
bits : 9 - 9 (1 bit)
access : read-write

MBRIF10 : MBRIF10
bits : 10 - 10 (1 bit)
access : read-write

MBRIF11 : MBRIF11
bits : 11 - 11 (1 bit)
access : read-write

MBRIF12 : MBRIF12
bits : 12 - 12 (1 bit)
access : read-write

MBRIF13 : MBRIF13
bits : 13 - 13 (1 bit)
access : read-write

MBRIF14 : MBRIF14
bits : 14 - 14 (1 bit)
access : read-write

MBRIF15 : MBRIF15
bits : 15 - 15 (1 bit)
access : read-write

MBRIF16 : MBRIF16
bits : 16 - 16 (1 bit)
access : read-write

MBRIF17 : MBRIF17
bits : 17 - 17 (1 bit)
access : read-write

MBRIF18 : MBRIF18
bits : 18 - 18 (1 bit)
access : read-write

MBRIF19 : MBRIF19
bits : 19 - 19 (1 bit)
access : read-write

MBRIF20 : MBRIF20
bits : 20 - 20 (1 bit)
access : read-write

MBRIF21 : MBRIF21
bits : 21 - 21 (1 bit)
access : read-write

MBRIF22 : MBRIF22
bits : 22 - 22 (1 bit)
access : read-write

MBRIF23 : MBRIF23
bits : 23 - 23 (1 bit)
access : read-write

MBRIF24 : MBRIF24
bits : 24 - 24 (1 bit)
access : read-write

MBRIF25 : MBRIF25
bits : 25 - 25 (1 bit)
access : read-write

MBRIF26 : MBRIF26
bits : 26 - 26 (1 bit)
access : read-write

MBRIF27 : MBRIF27
bits : 27 - 27 (1 bit)
access : read-write

MBRIF28 : MBRIF28
bits : 28 - 28 (1 bit)
access : read-write

MBRIF29 : MBRIF29
bits : 29 - 29 (1 bit)
access : read-write

MBRIF30 : MBRIF30
bits : 30 - 30 (1 bit)
access : read-write

MBRIF31 : MBRIF31
bits : 31 - 31 (1 bit)
access : read-write


MBIM

CAN Mailbox Interrupt Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBIM MBIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBIM0 MBIM1 MBIM2 MBIM3 MBIM4 MBIM5 MBIM6 MBIM7 MBIM8 MBIM9 MBIM10 MBIM11 MBIM12 MBIM13 MBIM14 MBIM15 MBIM16 MBIM17 MBIM18 MBIM19 MBIM20 MBIM21 MBIM22 MBIM23 MBIM24 MBIM25 MBIM26 MBIM27 MBIM28 MBIM29 MBIM30 MBIM31

MBIM0 : MBIM0
bits : 0 - 0 (1 bit)
access : read-write

MBIM1 : MBIM1
bits : 1 - 1 (1 bit)
access : read-write

MBIM2 : MBIM2
bits : 2 - 2 (1 bit)
access : read-write

MBIM3 : MBIM3
bits : 3 - 3 (1 bit)
access : read-write

MBIM4 : MBIM4
bits : 4 - 4 (1 bit)
access : read-write

MBIM5 : MBIM5
bits : 5 - 5 (1 bit)
access : read-write

MBIM6 : MBIM6
bits : 6 - 6 (1 bit)
access : read-write

MBIM7 : MBIM7
bits : 7 - 7 (1 bit)
access : read-write

MBIM8 : MBIM8
bits : 8 - 8 (1 bit)
access : read-write

MBIM9 : MBIM9
bits : 9 - 9 (1 bit)
access : read-write

MBIM10 : MBIM10
bits : 10 - 10 (1 bit)
access : read-write

MBIM11 : MBIM11
bits : 11 - 11 (1 bit)
access : read-write

MBIM12 : MBIM12
bits : 12 - 12 (1 bit)
access : read-write

MBIM13 : MBIM13
bits : 13 - 13 (1 bit)
access : read-write

MBIM14 : MBIM14
bits : 14 - 14 (1 bit)
access : read-write

MBIM15 : MBIM15
bits : 15 - 15 (1 bit)
access : read-write

MBIM16 : MBIM16
bits : 16 - 16 (1 bit)
access : read-write

MBIM17 : MBIM17
bits : 17 - 17 (1 bit)
access : read-write

MBIM18 : MBIM18
bits : 18 - 18 (1 bit)
access : read-write

MBIM19 : MBIM19
bits : 19 - 19 (1 bit)
access : read-write

MBIM20 : MBIM20
bits : 20 - 20 (1 bit)
access : read-write

MBIM21 : MBIM21
bits : 21 - 21 (1 bit)
access : read-write

MBIM22 : MBIM22
bits : 22 - 22 (1 bit)
access : read-write

MBIM23 : MBIM23
bits : 23 - 23 (1 bit)
access : read-write

MBIM24 : MBIM24
bits : 24 - 24 (1 bit)
access : read-write

MBIM25 : MBIM25
bits : 25 - 25 (1 bit)
access : read-write

MBIM26 : MBIM26
bits : 26 - 26 (1 bit)
access : read-write

MBIM27 : MBIM27
bits : 27 - 27 (1 bit)
access : read-write

MBIM28 : MBIM28
bits : 28 - 28 (1 bit)
access : read-write

MBIM29 : MBIM29
bits : 29 - 29 (1 bit)
access : read-write

MBIM30 : MBIM30
bits : 30 - 30 (1 bit)
access : read-write

MBIM31 : MBIM31
bits : 31 - 31 (1 bit)
access : read-write


CDR

CAN Change Data Request
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDR CDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDR0 CDR1 CDR2 CDR3 CDR4 CDR5 CDR6 CDR7 CDR8 CDR9 CDR10 CDR11 CDR12 CDR13 CDR14 CDR15 CDR16 CDR17 CDR18 CDR19 CDR20 CDR21 CDR22 CDR23 CDR24 CDR25 CDR26 CDR27 CDR28 CDR29 CDR30

CDR0 : CDR0
bits : 0 - 0 (1 bit)
access : read-write

CDR1 : CDR1
bits : 1 - 1 (1 bit)
access : read-write

CDR2 : CDR2
bits : 2 - 2 (1 bit)
access : read-write

CDR3 : CDR3
bits : 3 - 3 (1 bit)
access : read-write

CDR4 : CDR4
bits : 4 - 4 (1 bit)
access : read-write

CDR5 : CDR5
bits : 5 - 5 (1 bit)
access : read-write

CDR6 : CDR6
bits : 6 - 6 (1 bit)
access : read-write

CDR7 : CDR7
bits : 7 - 7 (1 bit)
access : read-write

CDR8 : CDR8
bits : 8 - 8 (1 bit)
access : read-write

CDR9 : CDR9
bits : 9 - 9 (1 bit)
access : read-write

CDR10 : CDR10
bits : 10 - 10 (1 bit)
access : read-write

CDR11 : CDR11
bits : 11 - 11 (1 bit)
access : read-write

CDR12 : CDR12
bits : 12 - 12 (1 bit)
access : read-write

CDR13 : CDR13
bits : 13 - 13 (1 bit)
access : read-write

CDR14 : CDR14
bits : 14 - 14 (1 bit)
access : read-write

CDR15 : CDR15
bits : 15 - 15 (1 bit)
access : read-write

CDR16 : CDR16
bits : 16 - 16 (1 bit)
access : read-write

CDR17 : CDR17
bits : 17 - 17 (1 bit)
access : read-write

CDR18 : CDR18
bits : 18 - 18 (1 bit)
access : read-write

CDR19 : CDR19
bits : 19 - 19 (1 bit)
access : read-write

CDR20 : CDR20
bits : 20 - 20 (1 bit)
access : read-write

CDR21 : CDR21
bits : 21 - 21 (1 bit)
access : read-write

CDR22 : CDR22
bits : 22 - 22 (1 bit)
access : read-write

CDR23 : CDR23
bits : 23 - 23 (1 bit)
access : read-write

CDR24 : CDR24
bits : 24 - 24 (1 bit)
access : read-write

CDR25 : CDR25
bits : 25 - 25 (1 bit)
access : read-write

CDR26 : CDR26
bits : 26 - 26 (1 bit)
access : read-write

CDR27 : CDR27
bits : 27 - 27 (1 bit)
access : read-write

CDR28 : CDR28
bits : 28 - 28 (1 bit)
access : read-write

CDR29 : CDR29
bits : 29 - 29 (1 bit)
access : read-write

CDR30 : CDR30
bits : 30 - 30 (1 bit)
access : read-write


RFP

CAN Remote Frame Pending Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFP RFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFP0 RFP1 RFP2 RFP3 RFP4 RFP5 RFP6 RFP7 RFP8 RFP9 RFP10 RFP11 RFP12 RFP13 RFP14 RFP15 RFP16 RFP17 RFP18 RFP19 RFP20 RFP21 RFP22 RFP23 RFP24 RFP25 RFP26 RFP27 RFP28 RFP29 RFP30 RFP31

RFP0 : RFP0
bits : 0 - 0 (1 bit)
access : read-write

RFP1 : RFP1
bits : 1 - 1 (1 bit)
access : read-write

RFP2 : RFP2
bits : 2 - 2 (1 bit)
access : read-write

RFP3 : RFP3
bits : 3 - 3 (1 bit)
access : read-write

RFP4 : RFP4
bits : 4 - 4 (1 bit)
access : read-write

RFP5 : RFP5
bits : 5 - 5 (1 bit)
access : read-write

RFP6 : RFP6
bits : 6 - 6 (1 bit)
access : read-write

RFP7 : RFP7
bits : 7 - 7 (1 bit)
access : read-write

RFP8 : RFP8
bits : 8 - 8 (1 bit)
access : read-write

RFP9 : RFP9
bits : 9 - 9 (1 bit)
access : read-write

RFP10 : RFP10
bits : 10 - 10 (1 bit)
access : read-write

RFP11 : RFP11
bits : 11 - 11 (1 bit)
access : read-write

RFP12 : RFP12
bits : 12 - 12 (1 bit)
access : read-write

RFP13 : RFP13
bits : 13 - 13 (1 bit)
access : read-write

RFP14 : RFP14
bits : 14 - 14 (1 bit)
access : read-write

RFP15 : RFP15
bits : 15 - 15 (1 bit)
access : read-write

RFP16 : RFP16
bits : 16 - 16 (1 bit)
access : read-write

RFP17 : RFP17
bits : 17 - 17 (1 bit)
access : read-write

RFP18 : RFP18
bits : 18 - 18 (1 bit)
access : read-write

RFP19 : RFP19
bits : 19 - 19 (1 bit)
access : read-write

RFP20 : RFP20
bits : 20 - 20 (1 bit)
access : read-write

RFP21 : RFP21
bits : 21 - 21 (1 bit)
access : read-write

RFP22 : RFP22
bits : 22 - 22 (1 bit)
access : read-write

RFP23 : RFP23
bits : 23 - 23 (1 bit)
access : read-write

RFP24 : RFP24
bits : 24 - 24 (1 bit)
access : read-write

RFP25 : RFP25
bits : 25 - 25 (1 bit)
access : read-write

RFP26 : RFP26
bits : 26 - 26 (1 bit)
access : read-write

RFP27 : RFP27
bits : 27 - 27 (1 bit)
access : read-write

RFP28 : RFP28
bits : 28 - 28 (1 bit)
access : read-write

RFP29 : RFP29
bits : 29 - 29 (1 bit)
access : read-write

RFP30 : RFP30
bits : 30 - 30 (1 bit)
access : read-write

RFP31 : RFP31
bits : 31 - 31 (1 bit)
access : read-write


CEC

CAN Error Counter Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEC CEC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REC TEC

REC : REC
bits : 0 - 7 (8 bit)
access : read-write

TEC : TEC
bits : 8 - 15 (8 bit)
access : read-write


TSP

CAN Time Stamp Counter Prescaler Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSP TSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSP

TSP : TSP
bits : 0 - 3 (4 bit)
access : read-write


TSC

CAN Time Stamp Counter Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSC TSC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSC

TSC : TSC
bits : 0 - 15 (16 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.