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UART0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :

Registers

SWRST

BRD

TRANS

DR

SR

FIFOCLR

ERR

CR0

CR1

CLK


SWRST

UART Software Reset Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWRST SWRST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST SWRSTF

SWRST : SWRST
bits : 0 - 1 (2 bit)
access : write-only

SWRSTF : SWRSTF
bits : 7 - 7 (1 bit)
access : read-only


BRD

UART Baud Rate Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRD BRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRN BRK KEN

BRN : BRN
bits : 0 - 15 (16 bit)
access : read-write

BRK : BRK
bits : 16 - 21 (6 bit)
access : read-write

KEN : KEN
bits : 23 - 23 (1 bit)
access : read-write


TRANS

UART Transfer Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRANS TRANS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXE TXE TXTRG BK

RXE : RXE
bits : 0 - 0 (1 bit)
access : read-write

TXE : TXE
bits : 1 - 1 (1 bit)
access : read-write

TXTRG : TXTRG
bits : 2 - 2 (1 bit)
access : read-write

BK : BK
bits : 3 - 3 (1 bit)
access : read-write


DR

UART Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR BERR FERR PERR

DR : DR
bits : 0 - 8 (9 bit)
access : read-write

BERR : BERR
bits : 16 - 16 (1 bit)
access : read-only

FERR : FERR
bits : 17 - 17 (1 bit)
access : read-only

PERR : PERR
bits : 18 - 18 (1 bit)
access : read-only


SR

UART Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLVL RXFF RXEND RXRUN TLVL TXFF TXEND TXRUN SUE

RLVL : RLVL
bits : 0 - 3 (4 bit)
access : read-only

RXFF : RXFF
bits : 5 - 5 (1 bit)
access : read-write

RXEND : RXEND
bits : 6 - 6 (1 bit)
access : read-write

RXRUN : RXRUN
bits : 7 - 7 (1 bit)
access : read-only

TLVL : TLVL
bits : 8 - 11 (4 bit)
access : read-only

TXFF : TXFF
bits : 13 - 13 (1 bit)
access : read-write

TXEND : TXEND
bits : 14 - 14 (1 bit)
access : read-write

TXRUN : TXRUN
bits : 15 - 15 (1 bit)
access : read-only

SUE : SUE
bits : 31 - 31 (1 bit)
access : read-only


FIFOCLR

UART FIFO Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FIFOCLR FIFOCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCLR TFCLR

RFCLR : RFCLR
bits : 0 - 0 (1 bit)
access : write-only

TFCLR : TFCLR
bits : 1 - 1 (1 bit)
access : write-only


ERR

UART Error Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERR ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERR FERR PERR OVRERR TRGERR

BERR : BERR
bits : 0 - 0 (1 bit)
access : read-write

FERR : FERR
bits : 1 - 1 (1 bit)
access : read-write

PERR : PERR
bits : 2 - 2 (1 bit)
access : read-write

OVRERR : OVRERR
bits : 3 - 3 (1 bit)
access : read-write

TRGERR : TRGERR
bits : 4 - 4 (1 bit)
access : read-write


CR0

UART Control Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM PE EVEN SBLEN DIR IV WU RTSE CTSE NF LPB HBSEN HBSMD HBSST

SM : SM
bits : 0 - 1 (2 bit)
access : read-write

PE : PE
bits : 2 - 2 (1 bit)
access : read-write

EVEN : EVEN
bits : 3 - 3 (1 bit)
access : read-write

SBLEN : SBLEN
bits : 4 - 4 (1 bit)
access : read-write

DIR : DIR
bits : 5 - 5 (1 bit)
access : read-write

IV : IV
bits : 6 - 6 (1 bit)
access : read-write

WU : WU
bits : 8 - 8 (1 bit)
access : read-write

RTSE : RTSE
bits : 9 - 9 (1 bit)
access : read-write

CTSE : CTSE
bits : 10 - 10 (1 bit)
access : read-write

NF : NF
bits : 12 - 14 (3 bit)
access : read-write

LPB : LPB
bits : 15 - 15 (1 bit)
access : read-write

HBSEN : HBSEN
bits : 16 - 16 (1 bit)
access : read-write

HBSMD : HBSMD
bits : 17 - 17 (1 bit)
access : read-write

HBSST : HBSST
bits : 18 - 18 (1 bit)
access : read-write


CR1

UART Control Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARE DMATE INTERR INTRXWE INTRXFE INTTXWE INTTXFE RIL TIL

DMARE : DMARE
bits : 0 - 0 (1 bit)
access : read-write

DMATE : DMATE
bits : 1 - 1 (1 bit)
access : read-write

INTERR : INTERR
bits : 2 - 2 (1 bit)
access : read-write

INTRXWE : INTRXWE
bits : 4 - 4 (1 bit)
access : read-write

INTRXFE : INTRXFE
bits : 5 - 5 (1 bit)
access : read-write

INTTXWE : INTTXWE
bits : 6 - 6 (1 bit)
access : read-write

INTTXFE : INTTXFE
bits : 7 - 7 (1 bit)
access : read-write

RIL : RIL
bits : 8 - 10 (3 bit)
access : read-write

TIL : TIL
bits : 12 - 14 (3 bit)
access : read-write


CLK

UART Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSEL

PRSEL : PRSEL
bits : 4 - 7 (4 bit)
access : read-write



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