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EI2C0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection :

Registers

ARST

ADBRT

ADBRR

ASR0

ASR1

APRS

ASCL

AAR1

AAR2

AIE

APM

AEN

ACR0

ACR1


ARST

EI2C Reset Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARST ARST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRES

SWRES : SWRES
bits : 0 - 1 (2 bit)
access : write-only


ADBRT

EI2C Transmit Data Buffer Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADBRT ADBRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBT

DBT : DBT
bits : 0 - 7 (8 bit)
access : read-write


ADBRR

EI2C Receive Data Buffer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADBRR ADBRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBR

DBR : DBR
bits : 0 - 7 (8 bit)
access : read-only


ASR0

EI2C Status Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASR0 ASR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKF BB TRX MST BC

ACKF : ACKF
bits : 0 - 0 (1 bit)
access : read-only

BB : BB
bits : 1 - 1 (1 bit)
access : read-only

TRX : TRX
bits : 2 - 2 (1 bit)
access : read-only

MST : MST
bits : 3 - 3 (1 bit)
access : read-only

BC : BC
bits : 4 - 7 (4 bit)
access : read-only


ASR1

EI2C Status Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASR1 ASR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCF RSCF SPCF TEND TBE RBF NACK AL GC AAS1 AAS2 EST ESP TOERR

STCF : STCF
bits : 0 - 0 (1 bit)
access : read-write

RSCF : RSCF
bits : 1 - 1 (1 bit)
access : read-write

SPCF : SPCF
bits : 2 - 2 (1 bit)
access : read-write

TEND : TEND
bits : 3 - 3 (1 bit)
access : read-write

TBE : TBE
bits : 4 - 4 (1 bit)
access : read-write

RBF : RBF
bits : 5 - 5 (1 bit)
access : read-write

NACK : NACK
bits : 6 - 6 (1 bit)
access : read-write

AL : AL
bits : 7 - 7 (1 bit)
access : read-write

GC : GC
bits : 8 - 8 (1 bit)
access : read-write

AAS1 : AAS1
bits : 9 - 9 (1 bit)
access : read-write

AAS2 : AAS2
bits : 10 - 10 (1 bit)
access : read-write

EST : EST
bits : 11 - 11 (1 bit)
access : read-write

ESP : ESP
bits : 12 - 12 (1 bit)
access : read-write

TOERR : TOERR
bits : 13 - 13 (1 bit)
access : read-write


APRS

EI2C Prescaler Clock Setting Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APRS APRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS

PRS : PRS
bits : 0 - 5 (6 bit)
access : read-write


ASCL

EI2C SCL Width Setting Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASCL ASCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLH SCLL

SCLH : SCLH
bits : 0 - 7 (8 bit)
access : read-write

SCLL : SCLL
bits : 8 - 15 (8 bit)
access : read-write


AAR1

EI2C First Slave Address Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AAR1 AAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA1E SA1 SAFS1

SA1E : SA1E
bits : 0 - 0 (1 bit)
access : read-write

SA1 : SA1
bits : 1 - 10 (10 bit)
access : read-write

SAFS1 : SAFS1
bits : 15 - 15 (1 bit)
access : read-write


AAR2

EI2C Second Slave Address Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AAR2 AAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA2E SA2 SAFS2

SA2E : SA2E
bits : 0 - 0 (1 bit)
access : read-write

SA2 : SA2
bits : 1 - 10 (10 bit)
access : read-write

SAFS2 : SAFS2
bits : 15 - 15 (1 bit)
access : read-write


AIE

EI2C Interrupt_DMA Setting Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AIE AIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSTE INTRSE INTSPE INTNACKE INTALE INTGCE INTASE INTESTE INTESPE INTTOE DMATX DMARX

INTSTE : INTSTE
bits : 0 - 0 (1 bit)
access : read-write

INTRSE : INTRSE
bits : 1 - 1 (1 bit)
access : read-write

INTSPE : INTSPE
bits : 2 - 2 (1 bit)
access : read-write

INTNACKE : INTNACKE
bits : 6 - 6 (1 bit)
access : read-write

INTALE : INTALE
bits : 7 - 7 (1 bit)
access : read-write

INTGCE : INTGCE
bits : 8 - 8 (1 bit)
access : read-write

INTASE : INTASE
bits : 9 - 9 (1 bit)
access : read-write

INTESTE : INTESTE
bits : 11 - 11 (1 bit)
access : read-write

INTESPE : INTESPE
bits : 12 - 12 (1 bit)
access : read-write

INTTOE : INTTOE
bits : 13 - 13 (1 bit)
access : read-write

DMATX : DMATX
bits : 14 - 14 (1 bit)
access : read-write

DMARX : DMARX
bits : 15 - 15 (1 bit)
access : read-write


APM

EI2C Bus Terminal Monitor Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

APM APM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCL SDA SCLOUT SDAOUT

SCL : SCL
bits : 0 - 0 (1 bit)
access : read-only

SDA : SDA
bits : 1 - 1 (1 bit)
access : read-only

SCLOUT : SCLOUT
bits : 2 - 2 (1 bit)
access : read-only

SDAOUT : SDAOUT
bits : 3 - 3 (1 bit)
access : read-only


AEN

EI2C Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AEN AEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2CM

I2CM : I2CM
bits : 0 - 0 (1 bit)
access : read-write


ACR0

EI2C Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR0 ACR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALE GCE NACKE ESTE ESPE TOE TOPER NFSEL DNF

ALE : ALE
bits : 0 - 0 (1 bit)
access : read-write

GCE : GCE
bits : 1 - 1 (1 bit)
access : read-write

NACKE : NACKE
bits : 2 - 2 (1 bit)
access : read-write

ESTE : ESTE
bits : 3 - 3 (1 bit)
access : read-write

ESPE : ESPE
bits : 4 - 4 (1 bit)
access : read-write

TOE : TOE
bits : 8 - 8 (1 bit)
access : read-write

TOPER : TOPER
bits : 9 - 10 (2 bit)
access : read-write

NFSEL : NFSEL
bits : 11 - 11 (1 bit)
access : read-write

DNF : DNF
bits : 12 - 14 (3 bit)
access : read-write


ACR1

EI2C Control Register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR1 ACR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST RS SP ACKSEL ACKWAIT OMC

ST : ST
bits : 0 - 0 (1 bit)
access : read-write

RS : RS
bits : 1 - 1 (1 bit)
access : read-write

SP : SP
bits : 2 - 2 (1 bit)
access : read-write

ACKSEL : ACKSEL
bits : 3 - 3 (1 bit)
access : read-write

ACKWAIT : ACKWAIT
bits : 4 - 4 (1 bit)
access : read-write

OMC : OMC
bits : 10 - 10 (1 bit)
access : read-write



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