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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

APB1RSTR

AHBENR

APB2ENR

APB1ENR

BDCR

CSR

AHBRSTR

CFGR2

CFGR3

CFGR

CIR

APB2RSTR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIRDY HSITRIM HSICAL HSEON HSERDY HSEBYP CSSON PLLON PLLRDY

HSION : Internal High Speed clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSIRDY : Internal High Speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSITRIM : Internal High Speed clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HSICAL : Internal High Speed clock Calibration
bits : 8 - 15 (8 bit)
access : read-only

HSEON : External High Speed clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : External High Speed clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : External High Speed clock Bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : Clock Security System enable
bits : 19 - 19 (1 bit)
access : read-write

PLLON : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


APB1RSTR

APB1 peripheral reset register (RCC_APB1RSTR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR APB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM3RST TIM4RST TIM6RST TIM7RST WWDGRST SPI2RST SPI3RST USART2RST USART3RST UART4RST UART5RST I2C1RST I2C2RST USBRST CANRST PWRRST DACRST I2C3RST

TIM2RST : Timer 2 reset
bits : 0 - 0 (1 bit)

TIM3RST : Timer 3 reset
bits : 1 - 1 (1 bit)

TIM4RST : Timer 14 reset
bits : 2 - 2 (1 bit)

TIM6RST : Timer 6 reset
bits : 4 - 4 (1 bit)

TIM7RST : Timer 7 reset
bits : 5 - 5 (1 bit)

WWDGRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

SPI3RST : SPI3 reset
bits : 15 - 15 (1 bit)

USART2RST : USART 2 reset
bits : 17 - 17 (1 bit)

USART3RST : USART3 reset
bits : 18 - 18 (1 bit)

UART4RST : UART 4 reset
bits : 19 - 19 (1 bit)

UART5RST : UART 5 reset
bits : 20 - 20 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

USBRST : USB reset
bits : 23 - 23 (1 bit)

CANRST : CAN reset
bits : 25 - 25 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DACRST : DAC interface reset
bits : 29 - 29 (1 bit)

I2C3RST : I2C3 reset
bits : 30 - 30 (1 bit)


AHBENR

AHB Peripheral Clock enable register (RCC_AHBENR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBENR AHBENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DMA2EN SRAMEN FLITFEN CRCEN IOPAEN IOPBEN IOPCEN IOPDEN IOPEEN IOPFEN TSCEN ADC12EN ADC34EN

DMAEN : DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2EN : DMA2 clock enable
bits : 1 - 1 (1 bit)

SRAMEN : SRAM interface clock enable
bits : 2 - 2 (1 bit)

FLITFEN : FLITF clock enable
bits : 4 - 4 (1 bit)

CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)

IOPAEN : I/O port A clock enable
bits : 17 - 17 (1 bit)

IOPBEN : I/O port B clock enable
bits : 18 - 18 (1 bit)

IOPCEN : I/O port C clock enable
bits : 19 - 19 (1 bit)

IOPDEN : I/O port D clock enable
bits : 20 - 20 (1 bit)

IOPEEN : I/O port E clock enable
bits : 21 - 21 (1 bit)

IOPFEN : I/O port F clock enable
bits : 22 - 22 (1 bit)

TSCEN : Touch sensing controller clock enable
bits : 24 - 24 (1 bit)

ADC12EN : ADC1 and ADC2 clock enable
bits : 28 - 28 (1 bit)

ADC34EN : ADC3 and ADC4 clock enable
bits : 29 - 29 (1 bit)


APB2ENR

APB2 peripheral clock enable register (RCC_APB2ENR)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN TIM1EN SPI1EN TIM8EN USART1EN TIM15EN TIM16EN TIM17EN

SYSCFGEN : SYSCFG clock enable
bits : 0 - 0 (1 bit)

TIM1EN : TIM1 Timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI 1 clock enable
bits : 12 - 12 (1 bit)

TIM8EN : TIM8 Timer clock enable
bits : 13 - 13 (1 bit)

USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)

TIM15EN : TIM15 timer clock enable
bits : 16 - 16 (1 bit)

TIM16EN : TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : TIM17 timer clock enable
bits : 18 - 18 (1 bit)


APB1ENR

APB1 peripheral clock enable register (RCC_APB1ENR)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR APB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM4EN TIM6EN TIM7EN WWDGEN SPI2EN SPI3EN USART2EN USART3EN UART4EN UART5EN I2C1EN I2C2EN USBEN CANEN PWREN DACEN I2C3EN

TIM2EN : Timer 2 clock enable
bits : 0 - 0 (1 bit)

TIM3EN : Timer 3 clock enable
bits : 1 - 1 (1 bit)

TIM4EN : Timer 4 clock enable
bits : 2 - 2 (1 bit)

TIM6EN : Timer 6 clock enable
bits : 4 - 4 (1 bit)

TIM7EN : Timer 7 clock enable
bits : 5 - 5 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI 2 clock enable
bits : 14 - 14 (1 bit)

SPI3EN : SPI 3 clock enable
bits : 15 - 15 (1 bit)

USART2EN : USART 2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART 3 clock enable
bits : 18 - 18 (1 bit)

UART4EN : UART 4 clock enable
bits : 19 - 19 (1 bit)

UART5EN : UART 5 clock enable
bits : 20 - 20 (1 bit)

I2C1EN : I2C 1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C 2 clock enable
bits : 22 - 22 (1 bit)

USBEN : USB clock enable
bits : 23 - 23 (1 bit)

CANEN : CAN clock enable
bits : 25 - 25 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)

I2C3EN : I2C 3 clock enable
bits : 30 - 30 (1 bit)


BDCR

Backup domain control register (RCC_BDCR)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP LSEDRV RTCSEL RTCEN BDRST

LSEON : External Low Speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : External Low Speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : External Low Speed oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

LSEDRV : LSE oscillator drive capability
bits : 3 - 4 (2 bit)
access : read-write

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write


CSR

Control/status register (RCC_CSR)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY RMVF OBLRSTF PINRSTF PORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSION : Internal low speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-write

PINRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

IWDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write


AHBRSTR

AHB peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRSTR AHBRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPARST IOPBRST IOPCRST IOPDRST IOPERST IOPFRST TSCRST ADC12RST ADC34RST

IOPARST : I/O port A reset
bits : 17 - 17 (1 bit)

IOPBRST : I/O port B reset
bits : 18 - 18 (1 bit)

IOPCRST : I/O port C reset
bits : 19 - 19 (1 bit)

IOPDRST : I/O port D reset
bits : 20 - 20 (1 bit)

IOPERST : I/O port E reset
bits : 21 - 21 (1 bit)

IOPFRST : I/O port F reset
bits : 22 - 22 (1 bit)

TSCRST : Touch sensing controller reset
bits : 24 - 24 (1 bit)

ADC12RST : ADC1 and ADC2 reset
bits : 28 - 28 (1 bit)

ADC34RST : ADC3 and ADC4 reset
bits : 29 - 29 (1 bit)


CFGR2

Clock configuration register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDIV ADC12PRES ADC34PRES

PREDIV : PREDIV division factor
bits : 0 - 3 (4 bit)

ADC12PRES : ADC1 and ADC2 prescaler
bits : 4 - 8 (5 bit)

ADC34PRES : ADC3 and ADC4 prescaler
bits : 9 - 13 (5 bit)


CFGR3

Clock configuration register 3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR3 CFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1SW I2C1SW I2C2SW I2C3SW TIM1SW TIM8SW USART2SW USART3SW UART4SW UART5SW

USART1SW : USART1 clock source selection
bits : 0 - 1 (2 bit)

I2C1SW : I2C1 clock source selection
bits : 4 - 4 (1 bit)

I2C2SW : I2C2 clock source selection
bits : 5 - 5 (1 bit)

I2C3SW : I2C3 clock source selection
bits : 6 - 6 (1 bit)

TIM1SW : Timer1 clock source selection
bits : 8 - 8 (1 bit)

TIM8SW : Timer8 clock source selection
bits : 9 - 9 (1 bit)

USART2SW : USART2 clock source selection
bits : 16 - 17 (2 bit)

USART3SW : USART3 clock source selection
bits : 18 - 19 (2 bit)

UART4SW : UART4 clock source selection
bits : 20 - 21 (2 bit)

UART5SW : UART5 clock source selection
bits : 22 - 23 (2 bit)


CFGR

Clock configuration register (RCC_CFGR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE1 PPRE2 PLLSRC PLLXTPRE PLLMUL USBPRES I2SSRC MCO MCOF

SW : System clock Switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System Clock Switch Status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : APB Low speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : APB high speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write

PLLSRC : PLL entry clock source
bits : 16 - 16 (1 bit)
access : read-write

PLLXTPRE : HSE divider for PLL entry
bits : 17 - 17 (1 bit)
access : read-write

PLLMUL : PLL Multiplication Factor
bits : 18 - 21 (4 bit)
access : read-write

USBPRES : USB prescaler
bits : 22 - 22 (1 bit)
access : read-write

I2SSRC : I2S external clock source selection
bits : 23 - 23 (1 bit)
access : read-write

MCO : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write

MCOF : Microcontroller Clock Output Flag
bits : 28 - 28 (1 bit)
access : read-only


CIR

Clock interrupt register (RCC_CIR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR CIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF PLLRDYF CSSF LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE LSIRDYC LSERDYC HSIRDYC HSERDYC PLLRDYC CSSC

LSIRDYF : LSI Ready Interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LSERDYF : LSE Ready Interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

HSIRDYF : HSI Ready Interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSE Ready Interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : PLL Ready Interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

CSSF : Clock Security System Interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSI Ready Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

LSERDYIE : LSE Ready Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

HSIRDYIE : HSI Ready Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSE Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : PLL Ready Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

LSIRDYC : LSI Ready Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

LSERDYC : LSE Ready Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only

HSIRDYC : HSI Ready Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSE Ready Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : PLL Ready Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only


APB2RSTR

APB2 peripheral reset register (RCC_APB2RSTR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGRST TIM1RST SPI1RST TIM8RST USART1RST TIM15RST TIM16RST TIM17RST

SYSCFGRST : SYSCFG and COMP reset
bits : 0 - 0 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

TIM8RST : TIM8 timer reset
bits : 13 - 13 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

TIM15RST : TIM15 timer reset
bits : 16 - 16 (1 bit)

TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)

TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)



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