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COMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

COMP1_CSR

COMP5_CSR

COMP6_CSR

COMP7_CSR

COMP2_CSR

COMP3_CSR

COMP4_CSR


COMP1_CSR

control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP1_CSR COMP1_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP1EN COMP1_INP_DAC COMP1MODE COMP1INSEL COMP1_OUT_SEL COMP1POL COMP1HYST COMP1_BLANKING COMP1OUT COMP1LOCK

COMP1EN : Comparator 1 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP1_INP_DAC : COMP1_INP_DAC
bits : 1 - 1 (1 bit)
access : read-write

COMP1MODE : Comparator 1 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP1INSEL : Comparator 1 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP1_OUT_SEL : Comparator 1 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP1POL : Comparator 1 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP1HYST : Comparator 1 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP1_BLANKING : Comparator 1 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP1OUT : Comparator 1 output
bits : 30 - 30 (1 bit)
access : read-only

COMP1LOCK : Comparator 1 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP5_CSR

control and status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP5_CSR COMP5_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP5EN COMP5MODE COMP5INSEL COMP5INPSEL COMP5_OUT_SEL COMP5POL COMP5HYST COMP5_BLANKING COMP5OUT COMP5LOCK

COMP5EN : Comparator 5 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP5MODE : Comparator 5 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP5INSEL : Comparator 5 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP5INPSEL : Comparator 5 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COMP5_OUT_SEL : Comparator 5 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP5POL : Comparator 5 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP5HYST : Comparator 5 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP5_BLANKING : Comparator 5 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP5OUT : Comparator51 output
bits : 30 - 30 (1 bit)
access : read-only

COMP5LOCK : Comparator 5 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP6_CSR

control and status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP6_CSR COMP6_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP6EN COMP6MODE COMP6INSEL COMP6INPSEL COM6WINMODE COMP6_OUT_SEL COMP6POL COMP6HYST COMP6_BLANKING COMP6OUT COMP6LOCK

COMP6EN : Comparator 6 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP6MODE : Comparator 6 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP6INSEL : Comparator 6 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP6INPSEL : Comparator 6 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COM6WINMODE : Comparator 6 window mode
bits : 9 - 9 (1 bit)
access : read-write

COMP6_OUT_SEL : Comparator 6 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP6POL : Comparator 6 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP6HYST : Comparator 6 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP6_BLANKING : Comparator 6 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP6OUT : Comparator 6 output
bits : 30 - 30 (1 bit)
access : read-only

COMP6LOCK : Comparator 6 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP7_CSR

control and status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP7_CSR COMP7_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP7EN COMP7MODE COMP7INSEL COMP7INPSEL COMP7_OUT_SEL COMP7POL COMP7HYST COMP7_BLANKING COMP7OUT COMP7LOCK

COMP7EN : Comparator 7 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP7MODE : Comparator 7 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP7INSEL : Comparator 7 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP7INPSEL : Comparator 7 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COMP7_OUT_SEL : Comparator 7 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP7POL : Comparator 7 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP7HYST : Comparator 7 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP7_BLANKING : Comparator 7 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP7OUT : Comparator 7 output
bits : 30 - 30 (1 bit)
access : read-only

COMP7LOCK : Comparator 7 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP2_CSR

control and status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP2_CSR COMP2_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP2EN COMP2MODE COMP2INSEL COMP2INPSEL COMP2INMSEL COMP2_OUT_SEL COMP2POL COMP2HYST COMP2_BLANKING COMP2OUT COMP2LOCK

COMP2EN : Comparator 2 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP2MODE : Comparator 2 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP2INSEL : Comparator 2 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP2INPSEL : Comparator 2 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COMP2INMSEL : Comparator 1inverting input selection
bits : 9 - 9 (1 bit)
access : read-write

COMP2_OUT_SEL : Comparator 2 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP2POL : Comparator 2 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP2HYST : Comparator 2 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP2_BLANKING : Comparator 2 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP2OUT : Comparator 2 output
bits : 30 - 30 (1 bit)
access : read-only

COMP2LOCK : Comparator 2 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP3_CSR

control and status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP3_CSR COMP3_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP3EN COMP3MODE COMP3INSEL COMP3INPSEL COMP3_OUT_SEL COMP3POL COMP3HYST COMP3_BLANKING COMP3OUT COMP3LOCK

COMP3EN : Comparator 3 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP3MODE : Comparator 3 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP3INSEL : Comparator 3 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP3INPSEL : Comparator 3 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COMP3_OUT_SEL : Comparator 3 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP3POL : Comparator 3 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP3HYST : Comparator 3 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP3_BLANKING : Comparator 3 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP3OUT : Comparator 3 output
bits : 30 - 30 (1 bit)
access : read-only

COMP3LOCK : Comparator 3 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP4_CSR

control and status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP4_CSR COMP4_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP4EN COMP4MODE COMP4INSEL COMP4INPSEL COM4WINMODE COMP4_OUT_SEL COMP4POL COMP4HYST COMP4_BLANKING COMP4OUT COMP4LOCK

COMP4EN : Comparator 4 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP4MODE : Comparator 4 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP4INSEL : Comparator 4 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP4INPSEL : Comparator 4 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COM4WINMODE : Comparator 4 window mode
bits : 9 - 9 (1 bit)
access : read-write

COMP4_OUT_SEL : Comparator 4 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP4POL : Comparator 4 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP4HYST : Comparator 4 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP4_BLANKING : Comparator 4 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP4OUT : Comparator 4 output
bits : 30 - 30 (1 bit)
access : read-only

COMP4LOCK : Comparator 4 lock
bits : 31 - 31 (1 bit)
access : read-write



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