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FPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1AC Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

Registers

CPACR

FPCCR

FPCAR

FPDSCR

MVFR0

MVFR1


CPACR

Coprocessor Access Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPACR CPACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP0 CP1 CP2 CP3 CP4 CP5 CP6 CP7 CP10 CP11

CP0 : Access privileges for coprocessor 0
bits : 0 - 0 (1 bit)

CP1 : Access privileges for coprocessor 1
bits : 2 - 2 (1 bit)

CP2 : Access privileges for coprocessor 2
bits : 4 - 4 (1 bit)

CP3 : Access privileges for coprocessor 3
bits : 6 - 6 (1 bit)

CP4 : Access privileges for coprocessor 4
bits : 8 - 8 (1 bit)

CP5 : Access privileges for coprocessor 5
bits : 10 - 10 (1 bit)

CP6 : Access privileges for coprocessor 6
bits : 12 - 13 (2 bit)

CP7 : Access privileges for coprocessor 7
bits : 14 - 14 (1 bit)

CP10 : Access privileges for coprocessor 10
bits : 20 - 20 (1 bit)

CP11 : Access privileges for coprocessor 11
bits : 22 - 22 (1 bit)


FPCCR

FP Context Control Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCCR FPCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSPACT USER THREAD HFRDY MMRDY BFRDY MONRDY LSPEN ASPEN

LSPACT : LSPACT
bits : 0 - 0 (1 bit)

USER : USER
bits : 1 - 1 (1 bit)

THREAD : THREAD
bits : 3 - 3 (1 bit)

HFRDY : HFRDY
bits : 4 - 4 (1 bit)

MMRDY : MMRDY
bits : 5 - 5 (1 bit)

BFRDY : BFRDY
bits : 6 - 6 (1 bit)

MONRDY : MONRDY
bits : 8 - 8 (1 bit)

LSPEN : LSPEN
bits : 30 - 30 (1 bit)

ASPEN : ASPEN
bits : 31 - 31 (1 bit)


FPCAR

FP Context Address Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCAR FPCAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : ADDRESS
bits : 3 - 31 (29 bit)


FPDSCR

FP Default Status Control Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPDSCR FPDSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMode FZ DN AHP

RMode : RMode
bits : 22 - 23 (2 bit)

FZ : FZ
bits : 24 - 24 (1 bit)

DN : DN
bits : 25 - 25 (1 bit)

AHP : AHP
bits : 26 - 26 (1 bit)


MVFR0

Media and VFP Feature Register 0
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MVFR0 MVFR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A_SIMD Single_precision Double_precision FP_exception_trapping Divide Square_root Short_vectors FP_rounding_modes

A_SIMD : A_SIMD registers
bits : 0 - 3 (4 bit)

Single_precision : Single_precision
bits : 4 - 7 (4 bit)

Double_precision : Double_precision
bits : 8 - 11 (4 bit)

FP_exception_trapping : FP exception trapping
bits : 12 - 15 (4 bit)

Divide : Divide
bits : 16 - 19 (4 bit)

Square_root : Square root
bits : 20 - 23 (4 bit)

Short_vectors : Short vectors
bits : 24 - 27 (4 bit)

FP_rounding_modes : FP rounding modes
bits : 28 - 31 (4 bit)


MVFR1

Media and VFP Feature Register 1
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MVFR1 MVFR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FtZ_mode D_NaN_mode FP_HPFP FP_fused_MAC

FtZ_mode : FtZ mode
bits : 0 - 3 (4 bit)

D_NaN_mode : D_NaN mode
bits : 4 - 7 (4 bit)

FP_HPFP : FP HPFP
bits : 24 - 27 (4 bit)

FP_fused_MAC : FP fused MAC
bits : 28 - 31 (4 bit)



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