Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
master control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : INRQ
bits : 0 - 0 (1 bit)
SLEEP : SLEEP
bits : 1 - 1 (1 bit)
TXFP : TXFP
bits : 2 - 2 (1 bit)
RFLM : RFLM
bits : 3 - 3 (1 bit)
NART : NART
bits : 4 - 4 (1 bit)
AWUM : AWUM
bits : 5 - 5 (1 bit)
ABOM : ABOM
bits : 6 - 6 (1 bit)
TTCM : TTCM
bits : 7 - 7 (1 bit)
RESET : RESET
bits : 15 - 15 (1 bit)
DBF : DBF
bits : 16 - 16 (1 bit)
receive FIFO 1 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMP1 : FMP1
bits : 0 - 1 (2 bit)
access : read-only
FULL1 : FULL1
bits : 3 - 3 (1 bit)
access : read-write
FOVR1 : FOVR1
bits : 4 - 4 (1 bit)
access : read-write
RFOM1 : RFOM1
bits : 5 - 5 (1 bit)
access : read-write
interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMEIE : TMEIE
bits : 0 - 0 (1 bit)
FMPIE0 : FMPIE0
bits : 1 - 1 (1 bit)
FFIE0 : FFIE0
bits : 2 - 2 (1 bit)
FOVIE0 : FOVIE0
bits : 3 - 3 (1 bit)
FMPIE1 : FMPIE1
bits : 4 - 4 (1 bit)
FFIE1 : FFIE1
bits : 5 - 5 (1 bit)
FOVIE1 : FOVIE1
bits : 6 - 6 (1 bit)
EWGIE : EWGIE
bits : 8 - 8 (1 bit)
EPVIE : EPVIE
bits : 9 - 9 (1 bit)
BOFIE : BOFIE
bits : 10 - 10 (1 bit)
LECIE : LECIE
bits : 11 - 11 (1 bit)
ERRIE : ERRIE
bits : 15 - 15 (1 bit)
WKUIE : WKUIE
bits : 16 - 16 (1 bit)
SLKIE : SLKIE
bits : 17 - 17 (1 bit)
error status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWGF : EWGF
bits : 0 - 0 (1 bit)
access : read-only
EPVF : EPVF
bits : 1 - 1 (1 bit)
access : read-only
BOFF : BOFF
bits : 2 - 2 (1 bit)
access : read-only
LEC : LEC
bits : 4 - 6 (3 bit)
access : read-write
TEC : TEC
bits : 16 - 23 (8 bit)
access : read-only
REC : REC
bits : 24 - 31 (8 bit)
access : read-only
TX mailbox identifier register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRQ : TXRQ
bits : 0 - 0 (1 bit)
RTR : RTR
bits : 1 - 1 (1 bit)
IDE : IDE
bits : 2 - 2 (1 bit)
EXID : EXID
bits : 3 - 20 (18 bit)
STID : STID
bits : 21 - 31 (11 bit)
mailbox data length control and time stamp register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC : DLC
bits : 0 - 3 (4 bit)
TGT : TGT
bits : 8 - 8 (1 bit)
TIME : TIME
bits : 16 - 31 (16 bit)
mailbox data low register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DATA0
bits : 0 - 7 (8 bit)
DATA1 : DATA1
bits : 8 - 15 (8 bit)
DATA2 : DATA2
bits : 16 - 23 (8 bit)
DATA3 : DATA3
bits : 24 - 31 (8 bit)
mailbox data high register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : DATA4
bits : 0 - 7 (8 bit)
DATA5 : DATA5
bits : 8 - 15 (8 bit)
DATA6 : DATA6
bits : 16 - 23 (8 bit)
DATA7 : DATA7
bits : 24 - 31 (8 bit)
TX mailbox identifier register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRQ : TXRQ
bits : 0 - 0 (1 bit)
RTR : RTR
bits : 1 - 1 (1 bit)
IDE : IDE
bits : 2 - 2 (1 bit)
EXID : EXID
bits : 3 - 20 (18 bit)
STID : STID
bits : 21 - 31 (11 bit)
mailbox data length control and time stamp register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC : DLC
bits : 0 - 3 (4 bit)
TGT : TGT
bits : 8 - 8 (1 bit)
TIME : TIME
bits : 16 - 31 (16 bit)
mailbox data low register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DATA0
bits : 0 - 7 (8 bit)
DATA1 : DATA1
bits : 8 - 15 (8 bit)
DATA2 : DATA2
bits : 16 - 23 (8 bit)
DATA3 : DATA3
bits : 24 - 31 (8 bit)
mailbox data high register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : DATA4
bits : 0 - 7 (8 bit)
DATA5 : DATA5
bits : 8 - 15 (8 bit)
DATA6 : DATA6
bits : 16 - 23 (8 bit)
DATA7 : DATA7
bits : 24 - 31 (8 bit)
TX mailbox identifier register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRQ : TXRQ
bits : 0 - 0 (1 bit)
RTR : RTR
bits : 1 - 1 (1 bit)
IDE : IDE
bits : 2 - 2 (1 bit)
EXID : EXID
bits : 3 - 20 (18 bit)
STID : STID
bits : 21 - 31 (11 bit)
mailbox data length control and time stamp register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC : DLC
bits : 0 - 3 (4 bit)
TGT : TGT
bits : 8 - 8 (1 bit)
TIME : TIME
bits : 16 - 31 (16 bit)
mailbox data low register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DATA0
bits : 0 - 7 (8 bit)
DATA1 : DATA1
bits : 8 - 15 (8 bit)
DATA2 : DATA2
bits : 16 - 23 (8 bit)
DATA3 : DATA3
bits : 24 - 31 (8 bit)
mailbox data high register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : DATA4
bits : 0 - 7 (8 bit)
DATA5 : DATA5
bits : 8 - 15 (8 bit)
DATA6 : DATA6
bits : 16 - 23 (8 bit)
DATA7 : DATA7
bits : 24 - 31 (8 bit)
receive FIFO mailbox identifier register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RTR : RTR
bits : 1 - 1 (1 bit)
IDE : IDE
bits : 2 - 2 (1 bit)
EXID : EXID
bits : 3 - 20 (18 bit)
STID : STID
bits : 21 - 31 (11 bit)
receive FIFO mailbox data length control and time stamp register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DLC : DLC
bits : 0 - 3 (4 bit)
FMI : FMI
bits : 8 - 15 (8 bit)
TIME : TIME
bits : 16 - 31 (16 bit)
receive FIFO mailbox data low register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DATA0
bits : 0 - 7 (8 bit)
DATA1 : DATA1
bits : 8 - 15 (8 bit)
DATA2 : DATA2
bits : 16 - 23 (8 bit)
DATA3 : DATA3
bits : 24 - 31 (8 bit)
receive FIFO mailbox data high register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : DATA4
bits : 0 - 7 (8 bit)
DATA5 : DATA5
bits : 8 - 15 (8 bit)
DATA6 : DATA6
bits : 16 - 23 (8 bit)
DATA7 : DATA7
bits : 24 - 31 (8 bit)
bit timing register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRP : BRP
bits : 0 - 9 (10 bit)
TS1 : TS1
bits : 16 - 19 (4 bit)
TS2 : TS2
bits : 20 - 22 (3 bit)
SJW : SJW
bits : 24 - 25 (2 bit)
LBKM : LBKM
bits : 30 - 30 (1 bit)
SILM : SILM
bits : 31 - 31 (1 bit)
receive FIFO mailbox identifier register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RTR : RTR
bits : 1 - 1 (1 bit)
IDE : IDE
bits : 2 - 2 (1 bit)
EXID : EXID
bits : 3 - 20 (18 bit)
STID : STID
bits : 21 - 31 (11 bit)
receive FIFO mailbox data length control and time stamp register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DLC : DLC
bits : 0 - 3 (4 bit)
FMI : FMI
bits : 8 - 15 (8 bit)
TIME : TIME
bits : 16 - 31 (16 bit)
receive FIFO mailbox data low register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DATA0
bits : 0 - 7 (8 bit)
DATA1 : DATA1
bits : 8 - 15 (8 bit)
DATA2 : DATA2
bits : 16 - 23 (8 bit)
DATA3 : DATA3
bits : 24 - 31 (8 bit)
receive FIFO mailbox data high register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : DATA4
bits : 0 - 7 (8 bit)
DATA5 : DATA5
bits : 8 - 15 (8 bit)
DATA6 : DATA6
bits : 16 - 23 (8 bit)
DATA7 : DATA7
bits : 24 - 31 (8 bit)
filter master register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINIT : Filter init mode
bits : 0 - 0 (1 bit)
CAN2SB : CAN2 start bank
bits : 8 - 13 (6 bit)
filter mode register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBM0 : Filter mode
bits : 0 - 0 (1 bit)
FBM1 : Filter mode
bits : 1 - 1 (1 bit)
FBM2 : Filter mode
bits : 2 - 2 (1 bit)
FBM3 : Filter mode
bits : 3 - 3 (1 bit)
FBM4 : Filter mode
bits : 4 - 4 (1 bit)
FBM5 : Filter mode
bits : 5 - 5 (1 bit)
FBM6 : Filter mode
bits : 6 - 6 (1 bit)
FBM7 : Filter mode
bits : 7 - 7 (1 bit)
FBM8 : Filter mode
bits : 8 - 8 (1 bit)
FBM9 : Filter mode
bits : 9 - 9 (1 bit)
FBM10 : Filter mode
bits : 10 - 10 (1 bit)
FBM11 : Filter mode
bits : 11 - 11 (1 bit)
FBM12 : Filter mode
bits : 12 - 12 (1 bit)
FBM13 : Filter mode
bits : 13 - 13 (1 bit)
FBM14 : Filter mode
bits : 14 - 14 (1 bit)
FBM15 : Filter mode
bits : 15 - 15 (1 bit)
FBM16 : Filter mode
bits : 16 - 16 (1 bit)
FBM17 : Filter mode
bits : 17 - 17 (1 bit)
FBM18 : Filter mode
bits : 18 - 18 (1 bit)
FBM19 : Filter mode
bits : 19 - 19 (1 bit)
FBM20 : Filter mode
bits : 20 - 20 (1 bit)
FBM21 : Filter mode
bits : 21 - 21 (1 bit)
FBM22 : Filter mode
bits : 22 - 22 (1 bit)
FBM23 : Filter mode
bits : 23 - 23 (1 bit)
FBM24 : Filter mode
bits : 24 - 24 (1 bit)
FBM25 : Filter mode
bits : 25 - 25 (1 bit)
FBM26 : Filter mode
bits : 26 - 26 (1 bit)
FBM27 : Filter mode
bits : 27 - 27 (1 bit)
filter scale register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSC0 : Filter scale configuration
bits : 0 - 0 (1 bit)
FSC1 : Filter scale configuration
bits : 1 - 1 (1 bit)
FSC2 : Filter scale configuration
bits : 2 - 2 (1 bit)
FSC3 : Filter scale configuration
bits : 3 - 3 (1 bit)
FSC4 : Filter scale configuration
bits : 4 - 4 (1 bit)
FSC5 : Filter scale configuration
bits : 5 - 5 (1 bit)
FSC6 : Filter scale configuration
bits : 6 - 6 (1 bit)
FSC7 : Filter scale configuration
bits : 7 - 7 (1 bit)
FSC8 : Filter scale configuration
bits : 8 - 8 (1 bit)
FSC9 : Filter scale configuration
bits : 9 - 9 (1 bit)
FSC10 : Filter scale configuration
bits : 10 - 10 (1 bit)
FSC11 : Filter scale configuration
bits : 11 - 11 (1 bit)
FSC12 : Filter scale configuration
bits : 12 - 12 (1 bit)
FSC13 : Filter scale configuration
bits : 13 - 13 (1 bit)
FSC14 : Filter scale configuration
bits : 14 - 14 (1 bit)
FSC15 : Filter scale configuration
bits : 15 - 15 (1 bit)
FSC16 : Filter scale configuration
bits : 16 - 16 (1 bit)
FSC17 : Filter scale configuration
bits : 17 - 17 (1 bit)
FSC18 : Filter scale configuration
bits : 18 - 18 (1 bit)
FSC19 : Filter scale configuration
bits : 19 - 19 (1 bit)
FSC20 : Filter scale configuration
bits : 20 - 20 (1 bit)
FSC21 : Filter scale configuration
bits : 21 - 21 (1 bit)
FSC22 : Filter scale configuration
bits : 22 - 22 (1 bit)
FSC23 : Filter scale configuration
bits : 23 - 23 (1 bit)
FSC24 : Filter scale configuration
bits : 24 - 24 (1 bit)
FSC25 : Filter scale configuration
bits : 25 - 25 (1 bit)
FSC26 : Filter scale configuration
bits : 26 - 26 (1 bit)
FSC27 : Filter scale configuration
bits : 27 - 27 (1 bit)
filter FIFO assignment register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FFA0 : Filter FIFO assignment for filter 0
bits : 0 - 0 (1 bit)
FFA1 : Filter FIFO assignment for filter 1
bits : 1 - 1 (1 bit)
FFA2 : Filter FIFO assignment for filter 2
bits : 2 - 2 (1 bit)
FFA3 : Filter FIFO assignment for filter 3
bits : 3 - 3 (1 bit)
FFA4 : Filter FIFO assignment for filter 4
bits : 4 - 4 (1 bit)
FFA5 : Filter FIFO assignment for filter 5
bits : 5 - 5 (1 bit)
FFA6 : Filter FIFO assignment for filter 6
bits : 6 - 6 (1 bit)
FFA7 : Filter FIFO assignment for filter 7
bits : 7 - 7 (1 bit)
FFA8 : Filter FIFO assignment for filter 8
bits : 8 - 8 (1 bit)
FFA9 : Filter FIFO assignment for filter 9
bits : 9 - 9 (1 bit)
FFA10 : Filter FIFO assignment for filter 10
bits : 10 - 10 (1 bit)
FFA11 : Filter FIFO assignment for filter 11
bits : 11 - 11 (1 bit)
FFA12 : Filter FIFO assignment for filter 12
bits : 12 - 12 (1 bit)
FFA13 : Filter FIFO assignment for filter 13
bits : 13 - 13 (1 bit)
FFA14 : Filter FIFO assignment for filter 14
bits : 14 - 14 (1 bit)
FFA15 : Filter FIFO assignment for filter 15
bits : 15 - 15 (1 bit)
FFA16 : Filter FIFO assignment for filter 16
bits : 16 - 16 (1 bit)
FFA17 : Filter FIFO assignment for filter 17
bits : 17 - 17 (1 bit)
FFA18 : Filter FIFO assignment for filter 18
bits : 18 - 18 (1 bit)
FFA19 : Filter FIFO assignment for filter 19
bits : 19 - 19 (1 bit)
FFA20 : Filter FIFO assignment for filter 20
bits : 20 - 20 (1 bit)
FFA21 : Filter FIFO assignment for filter 21
bits : 21 - 21 (1 bit)
FFA22 : Filter FIFO assignment for filter 22
bits : 22 - 22 (1 bit)
FFA23 : Filter FIFO assignment for filter 23
bits : 23 - 23 (1 bit)
FFA24 : Filter FIFO assignment for filter 24
bits : 24 - 24 (1 bit)
FFA25 : Filter FIFO assignment for filter 25
bits : 25 - 25 (1 bit)
FFA26 : Filter FIFO assignment for filter 26
bits : 26 - 26 (1 bit)
FFA27 : Filter FIFO assignment for filter 27
bits : 27 - 27 (1 bit)
CAN filter activation register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FACT0 : Filter active
bits : 0 - 0 (1 bit)
FACT1 : Filter active
bits : 1 - 1 (1 bit)
FACT2 : Filter active
bits : 2 - 2 (1 bit)
FACT3 : Filter active
bits : 3 - 3 (1 bit)
FACT4 : Filter active
bits : 4 - 4 (1 bit)
FACT5 : Filter active
bits : 5 - 5 (1 bit)
FACT6 : Filter active
bits : 6 - 6 (1 bit)
FACT7 : Filter active
bits : 7 - 7 (1 bit)
FACT8 : Filter active
bits : 8 - 8 (1 bit)
FACT9 : Filter active
bits : 9 - 9 (1 bit)
FACT10 : Filter active
bits : 10 - 10 (1 bit)
FACT11 : Filter active
bits : 11 - 11 (1 bit)
FACT12 : Filter active
bits : 12 - 12 (1 bit)
FACT13 : Filter active
bits : 13 - 13 (1 bit)
FACT14 : Filter active
bits : 14 - 14 (1 bit)
FACT15 : Filter active
bits : 15 - 15 (1 bit)
FACT16 : Filter active
bits : 16 - 16 (1 bit)
FACT17 : Filter active
bits : 17 - 17 (1 bit)
FACT18 : Filter active
bits : 18 - 18 (1 bit)
FACT19 : Filter active
bits : 19 - 19 (1 bit)
FACT20 : Filter active
bits : 20 - 20 (1 bit)
FACT21 : Filter active
bits : 21 - 21 (1 bit)
FACT22 : Filter active
bits : 22 - 22 (1 bit)
FACT23 : Filter active
bits : 23 - 23 (1 bit)
FACT24 : Filter active
bits : 24 - 24 (1 bit)
FACT25 : Filter active
bits : 25 - 25 (1 bit)
FACT26 : Filter active
bits : 26 - 26 (1 bit)
FACT27 : Filter active
bits : 27 - 27 (1 bit)
Filter bank 0 register 1
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB0 : Filter bits
bits : 0 - 0 (1 bit)
FB1 : Filter bits
bits : 1 - 1 (1 bit)
FB2 : Filter bits
bits : 2 - 2 (1 bit)
FB3 : Filter bits
bits : 3 - 3 (1 bit)
FB4 : Filter bits
bits : 4 - 4 (1 bit)
FB5 : Filter bits
bits : 5 - 5 (1 bit)
FB6 : Filter bits
bits : 6 - 6 (1 bit)
FB7 : Filter bits
bits : 7 - 7 (1 bit)
FB8 : Filter bits
bits : 8 - 8 (1 bit)
FB9 : Filter bits
bits : 9 - 9 (1 bit)
FB10 : Filter bits
bits : 10 - 10 (1 bit)
FB11 : Filter bits
bits : 11 - 11 (1 bit)
FB12 : Filter bits
bits : 12 - 12 (1 bit)
FB13 : Filter bits
bits : 13 - 13 (1 bit)
FB14 : Filter bits
bits : 14 - 14 (1 bit)
FB15 : Filter bits
bits : 15 - 15 (1 bit)
FB16 : Filter bits
bits : 16 - 16 (1 bit)
FB17 : Filter bits
bits : 17 - 17 (1 bit)
FB18 : Filter bits
bits : 18 - 18 (1 bit)
FB19 : Filter bits
bits : 19 - 19 (1 bit)
FB20 : Filter bits
bits : 20 - 20 (1 bit)
FB21 : Filter bits
bits : 21 - 21 (1 bit)
FB22 : Filter bits
bits : 22 - 22 (1 bit)
FB23 : Filter bits
bits : 23 - 23 (1 bit)
FB24 : Filter bits
bits : 24 - 24 (1 bit)
FB25 : Filter bits
bits : 25 - 25 (1 bit)
FB26 : Filter bits
bits : 26 - 26 (1 bit)
FB27 : Filter bits
bits : 27 - 27 (1 bit)
FB28 : Filter bits
bits : 28 - 28 (1 bit)
FB29 : Filter bits
bits : 29 - 29 (1 bit)
FB30 : Filter bits
bits : 30 - 30 (1 bit)
FB31 : Filter bits
bits : 31 - 31 (1 bit)
Filter bank 0 register 2
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB0 : Filter bits
bits : 0 - 0 (1 bit)
FB1 : Filter bits
bits : 1 - 1 (1 bit)
FB2 : Filter bits
bits : 2 - 2 (1 bit)
FB3 : Filter bits
bits : 3 - 3 (1 bit)
FB4 : Filter bits
bits : 4 - 4 (1 bit)
FB5 : Filter bits
bits : 5 - 5 (1 bit)
FB6 : Filter bits
bits : 6 - 6 (1 bit)
FB7 : Filter bits
bits : 7 - 7 (1 bit)
FB8 : Filter bits
bits : 8 - 8 (1 bit)
FB9 : Filter bits
bits : 9 - 9 (1 bit)
FB10 : Filter bits
bits : 10 - 10 (1 bit)
FB11 : Filter bits
bits : 11 - 11 (1 bit)
FB12 : Filter bits
bits : 12 - 12 (1 bit)
FB13 : Filter bits
bits : 13 - 13 (1 bit)
FB14 : Filter bits
bits : 14 - 14 (1 bit)
FB15 : Filter bits
bits : 15 - 15 (1 bit)
FB16 : Filter bits
bits : 16 - 16 (1 bit)
FB17 : Filter bits
bits : 17 - 17 (1 bit)
FB18 : Filter bits
bits : 18 - 18 (1 bit)
FB19 : Filter bits
bits : 19 - 19 (1 bit)
FB20 : Filter bits
bits : 20 - 20 (1 bit)
FB21 : Filter bits
bits : 21 - 21 (1 bit)
FB22 : Filter bits
bits : 22 - 22 (1 bit)
FB23 : Filter bits
bits : 23 - 23 (1 bit)
FB24 : Filter bits
bits : 24 - 24 (1 bit)
FB25 : Filter bits
bits : 25 - 25 (1 bit)
FB26 : Filter bits
bits : 26 - 26 (1 bit)
FB27 : Filter bits
bits : 27 - 27 (1 bit)
FB28 : Filter bits
bits : 28 - 28 (1 bit)
FB29 : Filter bits
bits : 29 - 29 (1 bit)
FB30 : Filter bits
bits : 30 - 30 (1 bit)
FB31 : Filter bits
bits : 31 - 31 (1 bit)
Filter bank 1 register 1
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB0 : Filter bits
bits : 0 - 0 (1 bit)
FB1 : Filter bits
bits : 1 - 1 (1 bit)
FB2 : Filter bits
bits : 2 - 2 (1 bit)
FB3 : Filter bits
bits : 3 - 3 (1 bit)
FB4 : Filter bits
bits : 4 - 4 (1 bit)
FB5 : Filter bits
bits : 5 - 5 (1 bit)
FB6 : Filter bits
bits : 6 - 6 (1 bit)
FB7 : Filter bits
bits : 7 - 7 (1 bit)
FB8 : Filter bits
bits : 8 - 8 (1 bit)
FB9 : Filter bits
bits : 9 - 9 (1 bit)
FB10 : Filter bits
bits : 10 - 10 (1 bit)
FB11 : Filter bits
bits : 11 - 11 (1 bit)
FB12 : Filter bits
bits : 12 - 12 (1 bit)
FB13 : Filter bits
bits : 13 - 13 (1 bit)
FB14 : Filter bits
bits : 14 - 14 (1 bit)
FB15 : Filter bits
bits : 15 - 15 (1 bit)
FB16 : Filter bits
bits : 16 - 16 (1 bit)
FB17 : Filter bits
bits : 17 - 17 (1 bit)
FB18 : Filter bits
bits : 18 - 18 (1 bit)
FB19 : Filter bits
bits : 19 - 19 (1 bit)
FB20 : Filter bits
bits : 20 - 20 (1 bit)
FB21 : Filter bits
bits : 21 - 21 (1 bit)
FB22 : Filter bits
bits : 22 - 22 (1 bit)
FB23 : Filter bits
bits : 23 - 23 (1 bit)
FB24 : Filter bits
bits : 24 - 24 (1 bit)
FB25 : Filter bits
bits : 25 - 25 (1 bit)
FB26 : Filter bits
bits : 26 - 26 (1 bit)
FB27 : Filter bits
bits : 27 - 27 (1 bit)
FB28 : Filter bits
bits : 28 - 28 (1 bit)
FB29 : Filter bits
bits : 29 - 29 (1 bit)
FB30 : Filter bits
bits : 30 - 30 (1 bit)
FB31 : Filter bits
bits : 31 - 31 (1 bit)
Filter bank 1 register 2
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB0 : Filter bits
bits : 0 - 0 (1 bit)
FB1 : Filter bits
bits : 1 - 1 (1 bit)
FB2 : Filter bits
bits : 2 - 2 (1 bit)
FB3 : Filter bits
bits : 3 - 3 (1 bit)
FB4 : Filter bits
bits : 4 - 4 (1 bit)
FB5 : Filter bits
bits : 5 - 5 (1 bit)
FB6 : Filter bits
bits : 6 - 6 (1 bit)
FB7 : Filter bits
bits : 7 - 7 (1 bit)
FB8 : Filter bits
bits : 8 - 8 (1 bit)
FB9 : Filter bits
bits : 9 - 9 (1 bit)
FB10 : Filter bits
bits : 10 - 10 (1 bit)
FB11 : Filter bits
bits : 11 - 11 (1 bit)
FB12 : Filter bits
bits : 12 - 12 (1 bit)
FB13 : Filter bits
bits : 13 - 13 (1 bit)
FB14 : Filter bits
bits : 14 - 14 (1 bit)
FB15 : Filter bits
bits : 15 - 15 (1 bit)
FB16 : Filter bits
bits : 16 - 16 (1 bit)
FB17 : Filter bits
bits : 17 - 17 (1 bit)
FB18 : Filter bits
bits : 18 - 18 (1 bit)
FB19 : Filter bits
bits : 19 - 19 (1 bit)
FB20 : Filter bits
bits : 20 - 20 (1 bit)
FB21 : Filter bits
bits : 21 - 21 (1 bit)
FB22 : Filter bits
bits : 22 - 22 (1 bit)
FB23 : Filter bits
bits : 23 - 23 (1 bit)
FB24 : Filter bits
bits : 24 - 24 (1 bit)
FB25 : Filter bits
bits : 25 - 25 (1 bit)
FB26 : Filter bits
bits : 26 - 26 (1 bit)
FB27 : Filter bits
bits : 27 - 27 (1 bit)
FB28 : Filter bits
bits : 28 - 28 (1 bit)
FB29 : Filter bits
bits : 29 - 29 (1 bit)
FB30 : Filter bits
bits : 30 - 30 (1 bit)
FB31 : Filter bits
bits : 31 - 31 (1 bit)
Filter bank 27 register 1
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB0 : Filter bits
bits : 0 - 0 (1 bit)
FB1 : Filter bits
bits : 1 - 1 (1 bit)
FB2 : Filter bits
bits : 2 - 2 (1 bit)
FB3 : Filter bits
bits : 3 - 3 (1 bit)
FB4 : Filter bits
bits : 4 - 4 (1 bit)
FB5 : Filter bits
bits : 5 - 5 (1 bit)
FB6 : Filter bits
bits : 6 - 6 (1 bit)
FB7 : Filter bits
bits : 7 - 7 (1 bit)
FB8 : Filter bits
bits : 8 - 8 (1 bit)
FB9 : Filter bits
bits : 9 - 9 (1 bit)
FB10 : Filter bits
bits : 10 - 10 (1 bit)
FB11 : Filter bits
bits : 11 - 11 (1 bit)
FB12 : Filter bits
bits : 12 - 12 (1 bit)
FB13 : Filter bits
bits : 13 - 13 (1 bit)
FB14 : Filter bits
bits : 14 - 14 (1 bit)
FB15 : Filter bits
bits : 15 - 15 (1 bit)
FB16 : Filter bits
bits : 16 - 16 (1 bit)
FB17 : Filter bits
bits : 17 - 17 (1 bit)
FB18 : Filter bits
bits : 18 - 18 (1 bit)
FB19 : Filter bits
bits : 19 - 19 (1 bit)
FB20 : Filter bits
bits : 20 - 20 (1 bit)
FB21 : Filter bits
bits : 21 - 21 (1 bit)
FB22 : Filter bits
bits : 22 - 22 (1 bit)
FB23 : Filter bits
bits : 23 - 23 (1 bit)
FB24 : Filter bits
bits : 24 - 24 (1 bit)
FB25 : Filter bits
bits : 25 - 25 (1 bit)
FB26 : Filter bits
bits : 26 - 26 (1 bit)
FB27 : Filter bits
bits : 27 - 27 (1 bit)
FB28 : Filter bits
bits : 28 - 28 (1 bit)
FB29 : Filter bits
bits : 29 - 29 (1 bit)
FB30 : Filter bits
bits : 30 - 30 (1 bit)
FB31 : Filter bits
bits : 31 - 31 (1 bit)
Filter bank 27 register 2
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB0 : Filter bits
bits : 0 - 0 (1 bit)
FB1 : Filter bits
bits : 1 - 1 (1 bit)
FB2 : Filter bits
bits : 2 - 2 (1 bit)
FB3 : Filter bits
bits : 3 - 3 (1 bit)
FB4 : Filter bits
bits : 4 - 4 (1 bit)
FB5 : Filter bits
bits : 5 - 5 (1 bit)
FB6 : Filter bits
bits : 6 - 6 (1 bit)
FB7 : Filter bits
bits : 7 - 7 (1 bit)
FB8 : Filter bits
bits : 8 - 8 (1 bit)
FB9 : Filter bits
bits : 9 - 9 (1 bit)
FB10 : Filter bits
bits : 10 - 10 (1 bit)
FB11 : Filter bits
bits : 11 - 11 (1 bit)
FB12 : Filter bits
bits : 12 - 12 (1 bit)
FB13 : Filter bits
bits : 13 - 13 (1 bit)
FB14 : Filter bits
bits : 14 - 14 (1 bit)
FB15 : Filter bits
bits : 15 - 15 (1 bit)
FB16 : Filter bits
bits : 16 - 16 (1 bit)
FB17 : Filter bits
bits : 17 - 17 (1 bit)
FB18 : Filter bits
bits : 18 - 18 (1 bit)
FB19 : Filter bits
bits : 19 - 19 (1 bit)
FB20 : Filter bits
bits : 20 - 20 (1 bit)
FB21 : Filter bits
bits : 21 - 21 (1 bit)
FB22 : Filter bits
bits : 22 - 22 (1 bit)
FB23 : Filter bits
bits : 23 - 23 (1 bit)
FB24 : Filter bits
bits : 24 - 24 (1 bit)
FB25 : Filter bits
bits : 25 - 25 (1 bit)
FB26 : Filter bits
bits : 26 - 26 (1 bit)
FB27 : Filter bits
bits : 27 - 27 (1 bit)
FB28 : Filter bits
bits : 28 - 28 (1 bit)
FB29 : Filter bits
bits : 29 - 29 (1 bit)
FB30 : Filter bits
bits : 30 - 30 (1 bit)
FB31 : Filter bits
bits : 31 - 31 (1 bit)
master status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INAK : INAK
bits : 0 - 0 (1 bit)
access : read-only
SLAK : SLAK
bits : 1 - 1 (1 bit)
access : read-only
ERRI : ERRI
bits : 2 - 2 (1 bit)
access : read-write
WKUI : WKUI
bits : 3 - 3 (1 bit)
access : read-write
SLAKI : SLAKI
bits : 4 - 4 (1 bit)
access : read-write
TXM : TXM
bits : 8 - 8 (1 bit)
access : read-only
RXM : RXM
bits : 9 - 9 (1 bit)
access : read-only
SAMP : SAMP
bits : 10 - 10 (1 bit)
access : read-only
RX : RX
bits : 11 - 11 (1 bit)
access : read-only
transmit status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQCP0 : RQCP0
bits : 0 - 0 (1 bit)
access : read-write
TXOK0 : TXOK0
bits : 1 - 1 (1 bit)
access : read-write
ALST0 : ALST0
bits : 2 - 2 (1 bit)
access : read-write
TERR0 : TERR0
bits : 3 - 3 (1 bit)
access : read-write
ABRQ0 : ABRQ0
bits : 7 - 7 (1 bit)
access : read-write
RQCP1 : RQCP1
bits : 8 - 8 (1 bit)
access : read-write
TXOK1 : TXOK1
bits : 9 - 9 (1 bit)
access : read-write
ALST1 : ALST1
bits : 10 - 10 (1 bit)
access : read-write
TERR1 : TERR1
bits : 11 - 11 (1 bit)
access : read-write
ABRQ1 : ABRQ1
bits : 15 - 15 (1 bit)
access : read-write
RQCP2 : RQCP2
bits : 16 - 16 (1 bit)
access : read-write
TXOK2 : TXOK2
bits : 17 - 17 (1 bit)
access : read-write
ALST2 : ALST2
bits : 18 - 18 (1 bit)
access : read-write
TERR2 : TERR2
bits : 19 - 19 (1 bit)
access : read-write
ABRQ2 : ABRQ2
bits : 23 - 23 (1 bit)
access : read-write
CODE : CODE
bits : 24 - 25 (2 bit)
access : read-only
TME0 : Lowest priority flag for mailbox 0
bits : 26 - 26 (1 bit)
access : read-only
TME1 : Lowest priority flag for mailbox 1
bits : 27 - 27 (1 bit)
access : read-only
TME2 : Lowest priority flag for mailbox 2
bits : 28 - 28 (1 bit)
access : read-only
LOW0 : Lowest priority flag for mailbox 0
bits : 29 - 29 (1 bit)
access : read-only
LOW1 : Lowest priority flag for mailbox 1
bits : 30 - 30 (1 bit)
access : read-only
LOW2 : Lowest priority flag for mailbox 2
bits : 31 - 31 (1 bit)
access : read-only
receive FIFO 0 register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMP0 : FMP0
bits : 0 - 1 (2 bit)
access : read-only
FULL0 : FULL0
bits : 3 - 3 (1 bit)
access : read-write
FOVR0 : FOVR0
bits : 4 - 4 (1 bit)
access : read-write
RFOM0 : RFOM0
bits : 5 - 5 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.