\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECEN : CEC Enable
bits : 0 - 0 (1 bit)
TXSOM : Tx start of message
bits : 1 - 1 (1 bit)
TXEOM : Tx End Of Message
bits : 2 - 2 (1 bit)
Interrupt and Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBR : Rx-Byte Received
bits : 0 - 0 (1 bit)
RXEND : End Of Reception
bits : 1 - 1 (1 bit)
RXOVR : Rx-Overrun
bits : 2 - 2 (1 bit)
BRE : Rx-Bit rising error
bits : 3 - 3 (1 bit)
SBPE : Rx-Short Bit period error
bits : 4 - 4 (1 bit)
LBPE : Rx-Long Bit Period Error
bits : 5 - 5 (1 bit)
RXACKE : Rx-Missing Acknowledge
bits : 6 - 6 (1 bit)
ARBLST : Arbitration Lost
bits : 7 - 7 (1 bit)
TXBR : Tx-Byte Request
bits : 8 - 8 (1 bit)
TXEND : End of Transmission
bits : 9 - 9 (1 bit)
TXUDR : Tx-Buffer Underrun
bits : 10 - 10 (1 bit)
TXERR : Tx-Error
bits : 11 - 11 (1 bit)
TXACKE : Tx-Missing acknowledge error
bits : 12 - 12 (1 bit)
interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBRIE : Rx-Byte Received Interrupt Enable
bits : 0 - 0 (1 bit)
RXENDIE : End Of Reception Interrupt Enable
bits : 1 - 1 (1 bit)
RXOVRIE : Rx-Buffer Overrun Interrupt Enable
bits : 2 - 2 (1 bit)
BREIE : Bit Rising Error Interrupt Enable
bits : 3 - 3 (1 bit)
SBPEIE : Short Bit Period Error Interrupt Enable
bits : 4 - 4 (1 bit)
LBPEIE : Long Bit Period Error Interrupt Enable
bits : 5 - 5 (1 bit)
RXACKIE : Rx-Missing Acknowledge Error Interrupt Enable
bits : 6 - 6 (1 bit)
ARBLSTIE : Arbitration Lost Interrupt Enable
bits : 7 - 7 (1 bit)
TXBRIE : Tx-Byte Request Interrupt Enable
bits : 8 - 8 (1 bit)
TXENDIE : Tx-End of message interrupt enable
bits : 9 - 9 (1 bit)
TXUDRIE : Tx-Underrun interrupt enable
bits : 10 - 10 (1 bit)
TXERRIE : Tx-Error Interrupt Enable
bits : 11 - 11 (1 bit)
TXACKIE : Tx-Missing Acknowledge Error Interrupt Enable
bits : 12 - 12 (1 bit)
configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFT : Signal Free Time
bits : 0 - 2 (3 bit)
RXTOL : Rx-Tolerance
bits : 3 - 3 (1 bit)
BRESTP : Rx-stop on bit rising error
bits : 4 - 4 (1 bit)
BREGEN : Generate error-bit on bit rising error
bits : 5 - 5 (1 bit)
LBPEGEN : Generate Error-Bit on Long Bit Period Error
bits : 6 - 6 (1 bit)
BRDNOGEN : Avoid Error-Bit Generation in Broadcast
bits : 7 - 7 (1 bit)
SFTOP : SFT Option Bit
bits : 8 - 8 (1 bit)
OAR : Own addresses configuration
bits : 16 - 30 (15 bit)
LSTN : Listen mode
bits : 31 - 31 (1 bit)
Tx data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXD : Tx Data register
bits : 0 - 7 (8 bit)
Rx Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDR : CEC Rx Data Register
bits : 0 - 7 (8 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.