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USB_OTG_HS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x500 byte (0x0)
mem_usage : registers
protection :

Registers

OTG_HS_DCFG

OTG_HS_DIEPMSK

OTG_HS_DIEPCTL0

OTG_HS_DIEPINT0

OTG_HS_DIEPTSIZ0

OTG_HS_DIEPDMA0

OTG_HS_DTXFSTS0

OTG_HS_DIEPCTL1

OTG_HS_DIEPINT1

OTG_HS_DIEPTSIZ1

OTG_HS_DIEPDMA1

OTG_HS_DTXFSTS1

OTG_HS_DOEPMSK

OTG_HS_DIEPCTL2

OTG_HS_DIEPINT2

OTG_HS_DIEPTSIZ2

OTG_HS_DIEPDMA2

OTG_HS_DTXFSTS2

OTG_HS_DIEPCTL3

OTG_HS_DIEPINT3

OTG_HS_DIEPTSIZ3

OTG_HS_DIEPDMA3

OTG_HS_DTXFSTS3

OTG_HS_DAINT

OTG_HS_DIEPCTL4

OTG_HS_DIEPINT4

OTG_HS_DIEPTSIZ4

OTG_HS_DIEPDMA4

OTG_HS_DTXFSTS4

OTG_HS_DIEPCTL5

OTG_HS_DIEPINT5

OTG_HS_DIEPTSIZ5

OTG_HS_DIEPDMA5

OTG_HS_DTXFSTS5

OTG_HS_DAINTMSK

OTG_HS_DIEPCTL6

OTG_HS_DIEPINT6

OTG_HS_DIEPTSIZ6

OTG_HS_DIEPDMA6

OTG_HS_DTXFSTS6

OTG_HS_DIEPCTL7

OTG_HS_DIEPINT7

OTG_HS_DIEPTSIZ7

OTG_HS_DIEPDMA7

OTG_HS_DTXFSTS7

OTG_HS_DIEPDMA8

OTG_HS_DIEPDMA9

OTG_HS_DIEPDMA10

OTG_HS_DIEPDMA11

OTG_HS_DVBUSDIS

OTG_HS_DIEPDMA12

OTG_HS_DIEPDMA13

OTG_HS_DVBUSPULSE

OTG_HS_DIEPDMA14

OTG_HS_DIEPDMA15

OTG_HS_DTHRCTL

OTG_HS_DOEPCTL0

OTG_HS_DOEPINT0

OTG_HS_DOEPTSIZ0

OTG_HS_DOEPDMA0

OTG_HS_DOEPCTL1

OTG_HS_DOEPINT1

OTG_HS_DOEPTSIZ1

OTG_HS_DOEPDMA1

OTG_HS_DIEPEMPMSK

OTG_HS_DOEPCTL2

OTG_HS_DOEPINT2

OTG_HS_DOEPTSIZ2

OTG_HS_DOEPDMA2

OTG_HS_DOEPCTL3

OTG_HS_DOEPINT3

OTG_HS_DOEPTSIZ3

OTG_HS_DOEPDMA3

OTG_HS_DEACHINT

OTG_HS_DOEPCTL4

OTG_HS_DOEPINT4

OTG_HS_DOEPTSIZ4

OTG_HS_DOEPDMA4

OTG_HS_DOEPCTL5

OTG_HS_DOEPINT5

OTG_HS_DOEPTSIZ5

OTG_HS_DOEPDMA5

OTG_HS_DEACHINTMSK

OTG_HS_DOEPCTL6

OTG_HS_DOEPINT6

OTG_HS_DOEPTSIZ6

OTG_HS_DOEPDMA6

OTG_HS_DOEPCTL7

OTG_HS_DOEPINT7

OTG_HS_DOEPTSIZ7

OTG_HS_DOEPDMA7

OTG_HS_DCTL

OTG_HS_DOEPDMA8

OTG_HS_DOEPDMA9

OTG_HS_DOEPDMA10

OTG_HS_DOEPDMA11

OTG_HS_DOEPDMA12

OTG_HS_DOEPDMA13

OTG_HS_DOEPDMA14

OTG_HS_DOEPDMA15

OTG_HS_DSTS


OTG_HS_DCFG

OTG_HS device configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DCFG OTG_HS_DCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSPD NZLSOHSK DAD PFIVL PERSCHIVL

DSPD : Device speed
bits : 0 - 1 (2 bit)

NZLSOHSK : Nonzero-length status OUT handshake
bits : 2 - 2 (1 bit)

DAD : Device address
bits : 4 - 10 (7 bit)

PFIVL : Periodic (micro)frame interval
bits : 11 - 12 (2 bit)

PERSCHIVL : Periodic scheduling interval
bits : 24 - 25 (2 bit)


OTG_HS_DIEPMSK

OTG_HS device IN endpoint common interrupt mask register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPMSK OTG_HS_DIEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM EPDM TOM ITTXFEMSK INEPNMM INEPNEM TXFURM BIM

XFRCM : Transfer completed interrupt mask
bits : 0 - 0 (1 bit)

EPDM : Endpoint disabled interrupt mask
bits : 1 - 1 (1 bit)

TOM : Timeout condition mask (nonisochronous endpoints)
bits : 3 - 3 (1 bit)

ITTXFEMSK : IN token received when TxFIFO empty mask
bits : 4 - 4 (1 bit)

INEPNMM : IN token received with EP mismatch mask
bits : 5 - 5 (1 bit)

INEPNEM : IN endpoint NAK effective mask
bits : 6 - 6 (1 bit)

TXFURM : FIFO underrun mask
bits : 8 - 8 (1 bit)

BIM : BNA interrupt mask
bits : 9 - 9 (1 bit)


OTG_HS_DIEPCTL0

OTG device endpoint-0 control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL0 OTG_HS_DIEPCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT0

OTG device endpoint-0 interrupt register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT0 OTG_HS_DIEPINT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ0

OTG_HS device IN endpoint 0 transfer size register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ0 OTG_HS_DIEPTSIZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT

XFRSIZ : Transfer size
bits : 0 - 6 (7 bit)

PKTCNT : Packet count
bits : 19 - 20 (2 bit)


OTG_HS_DIEPDMA0

OTG_HS device endpoint-1 DMA address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA0 OTG_HS_DIEPDMA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_DTXFSTS0

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS0 OTG_HS_DTXFSTS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DIEPCTL1

OTG device endpoint-1 control register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL1 OTG_HS_DIEPCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT1

OTG device endpoint-1 interrupt register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT1 OTG_HS_DIEPINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ1

OTG_HS device endpoint transfer size register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ1 OTG_HS_DIEPTSIZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

MCNT : Multi count
bits : 29 - 30 (2 bit)


OTG_HS_DIEPDMA1

OTG_HS device endpoint-2 DMA address register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA1 OTG_HS_DIEPDMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_DTXFSTS1

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS1 OTG_HS_DTXFSTS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DOEPMSK

OTG_HS device OUT endpoint common interrupt mask register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPMSK OTG_HS_DOEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM EPDM STUPM OTEPDM B2BSTUP OPEM BOIM

XFRCM : Transfer completed interrupt mask
bits : 0 - 0 (1 bit)

EPDM : Endpoint disabled interrupt mask
bits : 1 - 1 (1 bit)

STUPM : SETUP phase done mask
bits : 3 - 3 (1 bit)

OTEPDM : OUT token received when endpoint disabled mask
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received mask
bits : 6 - 6 (1 bit)

OPEM : OUT packet error mask
bits : 8 - 8 (1 bit)

BOIM : BNA interrupt mask
bits : 9 - 9 (1 bit)


OTG_HS_DIEPCTL2

OTG device endpoint-2 control register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL2 OTG_HS_DIEPCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT2

OTG device endpoint-2 interrupt register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT2 OTG_HS_DIEPINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ2

OTG_HS device endpoint transfer size register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ2 OTG_HS_DIEPTSIZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

MCNT : Multi count
bits : 29 - 30 (2 bit)


OTG_HS_DIEPDMA2

OTG_HS device endpoint-3 DMA address register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA2 OTG_HS_DIEPDMA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_DTXFSTS2

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS2 OTG_HS_DTXFSTS2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DIEPCTL3

OTG device endpoint-3 control register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL3 OTG_HS_DIEPCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT3

OTG device endpoint-3 interrupt register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT3 OTG_HS_DIEPINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ3

OTG_HS device endpoint transfer size register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ3 OTG_HS_DIEPTSIZ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

MCNT : Multi count
bits : 29 - 30 (2 bit)


OTG_HS_DIEPDMA3

OTG_HS device endpoint-4 DMA address register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA3 OTG_HS_DIEPDMA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_DTXFSTS3

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS3 OTG_HS_DTXFSTS3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DAINT

OTG_HS device all endpoints interrupt register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DAINT OTG_HS_DAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEPINT OEPINT

IEPINT : IN endpoint interrupt bits
bits : 0 - 15 (16 bit)

OEPINT : OUT endpoint interrupt bits
bits : 16 - 31 (16 bit)


OTG_HS_DIEPCTL4

OTG device endpoint-4 control register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL4 OTG_HS_DIEPCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT4

OTG device endpoint-4 interrupt register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT4 OTG_HS_DIEPINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ4

OTG_HS device endpoint transfer size register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ4 OTG_HS_DIEPTSIZ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

MCNT : Multi count
bits : 29 - 30 (2 bit)


OTG_HS_DIEPDMA4

OTG_HS device endpoint-5 DMA address register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA4 OTG_HS_DIEPDMA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_DTXFSTS4

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS4 OTG_HS_DTXFSTS4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DIEPCTL5

OTG device endpoint-5 control register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL5 OTG_HS_DIEPCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT5

OTG device endpoint-5 interrupt register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT5 OTG_HS_DIEPINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ5

OTG_HS device endpoint transfer size register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ5 OTG_HS_DIEPTSIZ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

MCNT : Multi count
bits : 29 - 30 (2 bit)


OTG_HS_DIEPDMA5

OTG Device channel-x DMA address register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA5 OTG_HS_DIEPDMA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DTXFSTS5

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS5 OTG_HS_DTXFSTS5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DAINTMSK

OTG_HS all endpoints interrupt mask register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DAINTMSK OTG_HS_DAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEPM OEPM

IEPM : IN EP interrupt mask bits
bits : 0 - 15 (16 bit)

OEPM : OUT EP interrupt mask bits
bits : 16 - 31 (16 bit)


OTG_HS_DIEPCTL6

OTG device endpoint-6 control register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL6 OTG_HS_DIEPCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT6

OTG device endpoint-6 interrupt register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT6 OTG_HS_DIEPINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ6

OTG_HS device endpoint transfer size register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ6 OTG_HS_DIEPTSIZ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

MCNT : Multi count
bits : 29 - 30 (2 bit)


OTG_HS_DIEPDMA6

OTG Device channel-x DMA address register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA6 OTG_HS_DIEPDMA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DTXFSTS6

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS6 OTG_HS_DTXFSTS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DIEPCTL7

OTG device endpoint-7 control register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPCTL7 OTG_HS_DIEPCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP Stall TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even/odd frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DIEPINT7

OTG device endpoint-7 interrupt register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPINT7 OTG_HS_DIEPINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS BERR NAK

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)
access : read-write

TOC : Timeout condition
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : IN token received when TxFIFO is empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNE : IN endpoint NAK effective
bits : 6 - 6 (1 bit)
access : read-write

TXFE : Transmit FIFO empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : Transmit Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

BNA : Buffer not available interrupt
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : Packet dropped status
bits : 11 - 11 (1 bit)
access : read-write

BERR : Babble error interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAK : NAK interrupt
bits : 13 - 13 (1 bit)
access : read-write


OTG_HS_DIEPTSIZ7

OTG_HS device endpoint transfer size register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPTSIZ7 OTG_HS_DIEPTSIZ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

MCNT : Multi count
bits : 29 - 30 (2 bit)


OTG_HS_DIEPDMA7

OTG Device channel-x DMA address register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA7 OTG_HS_DIEPDMA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DTXFSTS7

OTG_HS device IN endpoint transmit FIFO status register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTXFSTS7 OTG_HS_DTXFSTS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : IN endpoint TxFIFO space avail
bits : 0 - 15 (16 bit)


OTG_HS_DIEPDMA8

OTG Device channel-x DMA address register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA8 OTG_HS_DIEPDMA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DIEPDMA9

OTG Device channel-x DMA address register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA9 OTG_HS_DIEPDMA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DIEPDMA10

OTG Device channel-x DMA address register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA10 OTG_HS_DIEPDMA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DIEPDMA11

OTG Device channel-x DMA address register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA11 OTG_HS_DIEPDMA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DVBUSDIS

OTG_HS device VBUS discharge time register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DVBUSDIS OTG_HS_DVBUSDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSDT

VBUSDT : Device VBUS discharge time
bits : 0 - 15 (16 bit)


OTG_HS_DIEPDMA12

OTG Device channel-x DMA address register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA12 OTG_HS_DIEPDMA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DIEPDMA13

OTG Device channel-x DMA address register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA13 OTG_HS_DIEPDMA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DVBUSPULSE

OTG_HS device VBUS pulsing time register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DVBUSPULSE OTG_HS_DVBUSPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVBUSP

DVBUSP : Device VBUS pulsing time
bits : 0 - 11 (12 bit)


OTG_HS_DIEPDMA14

OTG Device channel-x DMA address register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA14 OTG_HS_DIEPDMA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DIEPDMA15

OTG Device channel-x DMA address register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPDMA15 OTG_HS_DIEPDMA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DTHRCTL

OTG_HS Device threshold control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DTHRCTL OTG_HS_DTHRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONISOTHREN ISOTHREN TXTHRLEN RXTHREN RXTHRLEN ARPEN

NONISOTHREN : Nonisochronous IN endpoints threshold enable
bits : 0 - 0 (1 bit)

ISOTHREN : ISO IN endpoint threshold enable
bits : 1 - 1 (1 bit)

TXTHRLEN : Transmit threshold length
bits : 2 - 10 (9 bit)

RXTHREN : Receive threshold enable
bits : 16 - 16 (1 bit)

RXTHRLEN : Receive threshold length
bits : 17 - 25 (9 bit)

ARPEN : Arbiter parking enable
bits : 27 - 27 (1 bit)


OTG_HS_DOEPCTL0

OTG_HS device control OUT endpoint 0 control register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL0 OTG_HS_DOEPCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP NAKSTS EPTYP SNPM Stall CNAK SNAK EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 1 (2 bit)
access : read-only

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-only

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-only

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : write-only


OTG_HS_DOEPINT0

OTG_HS device endpoint-0 interrupt register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT0 OTG_HS_DOEPINT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ0

OTG_HS device endpoint-0 transfer size register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ0 OTG_HS_DOEPTSIZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT STUPCNT

XFRSIZ : Transfer size
bits : 0 - 6 (7 bit)

PKTCNT : Packet count
bits : 19 - 19 (1 bit)

STUPCNT : SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA0

OTG Device channel-x DMA address register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA0 OTG_HS_DOEPDMA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPCTL1

OTG device endpoint-1 control register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL1 OTG_HS_DOEPCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP SNPM Stall CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even odd frame/Endpoint data PID
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID/Set even frame
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DOEPINT1

OTG_HS device endpoint-1 interrupt register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT1 OTG_HS_DOEPINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ1

OTG_HS device endpoint-1 transfer size register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ1 OTG_HS_DOEPTSIZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : Received data PID/SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA1

OTG Device channel-x DMA address register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA1 OTG_HS_DOEPDMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DIEPEMPMSK

OTG_HS device IN endpoint FIFO empty interrupt mask register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DIEPEMPMSK OTG_HS_DIEPEMPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXFEM

INEPTXFEM : IN EP Tx FIFO empty interrupt mask bits
bits : 0 - 15 (16 bit)


OTG_HS_DOEPCTL2

OTG device endpoint-2 control register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL2 OTG_HS_DOEPCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP SNPM Stall CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even odd frame/Endpoint data PID
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID/Set even frame
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DOEPINT2

OTG_HS device endpoint-2 interrupt register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT2 OTG_HS_DOEPINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ2

OTG_HS device endpoint-2 transfer size register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ2 OTG_HS_DOEPTSIZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : Received data PID/SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA2

OTG Device channel-x DMA address register
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA2 OTG_HS_DOEPDMA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPCTL3

OTG device endpoint-3 control register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL3 OTG_HS_DOEPCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP SNPM Stall CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even odd frame/Endpoint data PID
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID/Set even frame
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DOEPINT3

OTG_HS device endpoint-3 interrupt register
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT3 OTG_HS_DOEPINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ3

OTG_HS device endpoint-3 transfer size register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ3 OTG_HS_DOEPTSIZ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : Received data PID/SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA3

OTG Device channel-x DMA address register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA3 OTG_HS_DOEPDMA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DEACHINT

OTG_HS device each endpoint interrupt register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DEACHINT OTG_HS_DEACHINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEP1INT OEP1INT

IEP1INT : IN endpoint 1interrupt bit
bits : 1 - 1 (1 bit)

OEP1INT : OUT endpoint 1 interrupt bit
bits : 17 - 17 (1 bit)


OTG_HS_DOEPCTL4

OTG device endpoint-4 control register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL4 OTG_HS_DOEPCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP SNPM Stall CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even odd frame/Endpoint data PID
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID/Set even frame
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DOEPINT4

OTG_HS device endpoint-4 interrupt register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT4 OTG_HS_DOEPINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ4

OTG_HS device endpoint-4 transfer size register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ4 OTG_HS_DOEPTSIZ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : Received data PID/SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA4

OTG Device channel-x DMA address register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA4 OTG_HS_DOEPDMA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPCTL5

OTG device endpoint-5 control register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL5 OTG_HS_DOEPCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP SNPM Stall CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even odd frame/Endpoint data PID
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID/Set even frame
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DOEPINT5

OTG_HS device endpoint-5 interrupt register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT5 OTG_HS_DOEPINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ5

OTG_HS device endpoint-5 transfer size register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ5 OTG_HS_DOEPTSIZ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : Received data PID/SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA5

OTG Device channel-x DMA address register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA5 OTG_HS_DOEPDMA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DEACHINTMSK

OTG_HS device each endpoint interrupt register mask
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DEACHINTMSK OTG_HS_DEACHINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEP1INTM OEP1INTM

IEP1INTM : IN Endpoint 1 interrupt mask bit
bits : 1 - 1 (1 bit)

OEP1INTM : OUT Endpoint 1 interrupt mask bit
bits : 17 - 17 (1 bit)


OTG_HS_DOEPCTL6

OTG device endpoint-6 control register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL6 OTG_HS_DOEPCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP SNPM Stall CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even odd frame/Endpoint data PID
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID/Set even frame
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DOEPINT6

OTG_HS device endpoint-6 interrupt register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT6 OTG_HS_DOEPINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ6

OTG_HS device endpoint-6 transfer size register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ6 OTG_HS_DOEPTSIZ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : Received data PID/SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA6

OTG Device channel-x DMA address register
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA6 OTG_HS_DOEPDMA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPCTL7

OTG device endpoint-7 control register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPCTL7 OTG_HS_DOEPCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPID NAKSTS EPTYP SNPM Stall CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USB active endpoint
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPID : Even odd frame/Endpoint data PID
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK status
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
access : read-write

SNPM : Snoop mode
bits : 20 - 20 (1 bit)
access : read-write

Stall : STALL handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : Set DATA0 PID/Set even frame
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : Set odd frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint enable
bits : 31 - 31 (1 bit)
access : read-write


OTG_HS_DOEPINT7

OTG_HS device endpoint-7 interrupt register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPINT7 OTG_HS_DOEPINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD STUP OTEPDIS B2BSTUP NYET

XFRC : Transfer completed interrupt
bits : 0 - 0 (1 bit)

EPDISD : Endpoint disabled interrupt
bits : 1 - 1 (1 bit)

STUP : SETUP phase done
bits : 3 - 3 (1 bit)

OTEPDIS : OUT token received when endpoint disabled
bits : 4 - 4 (1 bit)

B2BSTUP : Back-to-back SETUP packets received
bits : 6 - 6 (1 bit)

NYET : NYET interrupt
bits : 14 - 14 (1 bit)


OTG_HS_DOEPTSIZ7

OTG_HS device endpoint-7 transfer size register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPTSIZ7 OTG_HS_DOEPTSIZ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : Received data PID/SETUP packet count
bits : 29 - 30 (2 bit)


OTG_HS_DOEPDMA7

OTG Device channel-x DMA address register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA7 OTG_HS_DOEPDMA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DCTL

OTG_HS device control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DCTL OTG_HS_DCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWUSIG SDIS GINSTS GONSTS TCTL SGINAK CGINAK SGONAK CGONAK POPRGDNE

RWUSIG : Remote wakeup signaling
bits : 0 - 0 (1 bit)
access : read-write

SDIS : Soft disconnect
bits : 1 - 1 (1 bit)
access : read-write

GINSTS : Global IN NAK status
bits : 2 - 2 (1 bit)
access : read-only

GONSTS : Global OUT NAK status
bits : 3 - 3 (1 bit)
access : read-only

TCTL : Test control
bits : 4 - 6 (3 bit)
access : read-write

SGINAK : Set global IN NAK
bits : 7 - 7 (1 bit)
access : write-only

CGINAK : Clear global IN NAK
bits : 8 - 8 (1 bit)
access : write-only

SGONAK : Set global OUT NAK
bits : 9 - 9 (1 bit)
access : write-only

CGONAK : Clear global OUT NAK
bits : 10 - 10 (1 bit)
access : write-only

POPRGDNE : Power-on programming done
bits : 11 - 11 (1 bit)
access : read-write


OTG_HS_DOEPDMA8

OTG Device channel-x DMA address register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA8 OTG_HS_DOEPDMA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPDMA9

OTG Device channel-x DMA address register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA9 OTG_HS_DOEPDMA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPDMA10

OTG Device channel-x DMA address register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA10 OTG_HS_DOEPDMA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPDMA11

OTG Device channel-x DMA address register
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA11 OTG_HS_DOEPDMA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPDMA12

OTG Device channel-x DMA address register
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA12 OTG_HS_DOEPDMA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPDMA13

OTG Device channel-x DMA address register
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA13 OTG_HS_DOEPDMA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPDMA14

OTG Device channel-x DMA address register
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA14 OTG_HS_DOEPDMA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DOEPDMA15

OTG Device channel-x DMA address register
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DOEPDMA15 OTG_HS_DOEPDMA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OTG_HS_DSTS

OTG_HS device status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_DSTS OTG_HS_DSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPSTS ENUMSPD EERR FNSOF

SUSPSTS : Suspend status
bits : 0 - 0 (1 bit)

ENUMSPD : Enumerated speed
bits : 1 - 2 (2 bit)

EERR : Erratic error
bits : 3 - 3 (1 bit)

FNSOF : Frame number of the received SOF
bits : 8 - 21 (14 bit)



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