\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
IDCODE
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : DEV_ID
bits : 0 - 11 (12 bit)
REV_ID : REV_ID
bits : 16 - 31 (16 bit)
Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_SLEEP : DBG_SLEEP
bits : 0 - 0 (1 bit)
DBG_STOP : DBG_STOP
bits : 1 - 1 (1 bit)
DBG_STANDBY : DBG_STANDBY
bits : 2 - 2 (1 bit)
TRACE_IOEN : TRACE_IOEN
bits : 5 - 5 (1 bit)
TRACE_MODE : TRACE_MODE
bits : 6 - 7 (2 bit)
Debug MCU APB1 Freeze registe
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM2_STOP : DBG_TIM2_STOP
bits : 0 - 0 (1 bit)
DBG_TIM3_STOP : DBG_TIM3 _STOP
bits : 1 - 1 (1 bit)
DBG_TIM4_STOP : DBG_TIM4_STOP
bits : 2 - 2 (1 bit)
DBG_TIM5_STOP : DBG_TIM5_STOP
bits : 3 - 3 (1 bit)
DBG_TIM6_STOP : DBG_TIM6_STOP
bits : 4 - 4 (1 bit)
DBG_TIM7_STOP : DBG_TIM7_STOP
bits : 5 - 5 (1 bit)
DBG_TIM12_STOP : DBG_TIM12_STOP
bits : 6 - 6 (1 bit)
DBG_TIM13_STOP : DBG_TIM13_STOP
bits : 7 - 7 (1 bit)
DBG_TIM14_STOP : DBG_TIM14_STOP
bits : 8 - 8 (1 bit)
DBG_WWDG_STOP : DBG_WWDG_STOP
bits : 11 - 11 (1 bit)
DBG_IWDEG_STOP : DBG_IWDEG_STOP
bits : 12 - 12 (1 bit)
DBG_J2C1_SMBUS_TIMEOUT : DBG_J2C1_SMBUS_TIMEOUT
bits : 21 - 21 (1 bit)
DBG_J2C2_SMBUS_TIMEOUT : DBG_J2C2_SMBUS_TIMEOUT
bits : 22 - 22 (1 bit)
DBG_J2C3SMBUS_TIMEOUT : DBG_J2C3SMBUS_TIMEOUT
bits : 23 - 23 (1 bit)
DBG_CAN1_STOP : DBG_CAN1_STOP
bits : 25 - 25 (1 bit)
DBG_CAN2_STOP : DBG_CAN2_STOP
bits : 26 - 26 (1 bit)
Debug MCU APB2 Freeze registe
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM1_STOP : TIM1 counter stopped when core is halted
bits : 0 - 0 (1 bit)
DBG_TIM8_STOP : TIM8 counter stopped when core is halted
bits : 1 - 1 (1 bit)
DBG_TIM9_STOP : TIM9 counter stopped when core is halted
bits : 16 - 16 (1 bit)
DBG_TIM10_STOP : TIM10 counter stopped when core is halted
bits : 17 - 17 (1 bit)
DBG_TIM11_STOP : TIM11 counter stopped when core is halted
bits : 18 - 18 (1 bit)
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