\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1 : DAC channel1 enable
bits : 0 - 0 (1 bit)
BOFF1 : DAC channel1 output buffer disable
bits : 1 - 1 (1 bit)
TEN1 : DAC channel1 trigger enable
bits : 2 - 2 (1 bit)
TSEL1 : DAC channel1 trigger selection
bits : 3 - 5 (3 bit)
WAVE1 : DAC channel1 noise/triangle wave generation enable
bits : 6 - 7 (2 bit)
MAMP1 : DAC channel1 mask/amplitude selector
bits : 8 - 11 (4 bit)
DMAEN1 : DAC channel1 DMA enable
bits : 12 - 12 (1 bit)
DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable
bits : 13 - 13 (1 bit)
EN2 : DAC channel2 enable
bits : 16 - 16 (1 bit)
BOFF2 : DAC channel2 output buffer disable
bits : 17 - 17 (1 bit)
TEN2 : DAC channel2 trigger enable
bits : 18 - 18 (1 bit)
TSEL2 : DAC channel2 trigger selection
bits : 19 - 21 (3 bit)
WAVE2 : DAC channel2 noise/triangle wave generation enable
bits : 22 - 23 (2 bit)
MAMP2 : DAC channel2 mask/amplitude selector
bits : 24 - 27 (4 bit)
DMAEN2 : DAC channel2 DMA enable
bits : 28 - 28 (1 bit)
DMAUDRIE2 : DAC channel2 DMA underrun interrupt enable
bits : 29 - 29 (1 bit)
channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)
channel2 12-bit right aligned data holding register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 12-bit right-aligned data
bits : 0 - 11 (12 bit)
channel2 12-bit left aligned data holding register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 12-bit left-aligned data
bits : 4 - 15 (12 bit)
channel2 8-bit right-aligned data holding register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 8-bit right-aligned data
bits : 0 - 7 (8 bit)
Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)
DACC2DHR : DAC channel2 12-bit right-aligned data
bits : 16 - 27 (12 bit)
DUAL DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)
DACC2DHR : DAC channel2 12-bit left-aligned data
bits : 20 - 31 (12 bit)
DUAL DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)
DACC2DHR : DAC channel2 8-bit right-aligned data
bits : 8 - 15 (8 bit)
channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC1DOR : DAC channel1 data output
bits : 0 - 11 (12 bit)
channel2 data output register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC2DOR : DAC channel2 data output
bits : 0 - 11 (12 bit)
status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAUDR1 : DAC channel1 DMA underrun flag
bits : 13 - 13 (1 bit)
DMAUDR2 : DAC channel2 DMA underrun flag
bits : 29 - 29 (1 bit)
software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRIG1 : DAC channel1 software trigger
bits : 0 - 0 (1 bit)
SWTRIG2 : DAC channel2 software trigger
bits : 1 - 1 (1 bit)
channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)
channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)
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