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FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ACR

CR

OPTCR

OPTCR1

KEYR

OPTKEYR

SR


ACR

Flash access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY PRFTEN ARTEN ARTRST

LATENCY : Latency
bits : 0 - 3 (4 bit)

PRFTEN : Prefetch enable
bits : 8 - 8 (1 bit)

ARTEN : ART Accelerator Enable
bits : 9 - 9 (1 bit)

ARTRST : ART Accelerator reset
bits : 11 - 11 (1 bit)


CR

Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG SER MER SNB PSIZE MER1 STRT EOPIE ERRIE LOCK

PG : Programming
bits : 0 - 0 (1 bit)

SER : Sector Erase
bits : 1 - 1 (1 bit)

MER : Mass Erase of sectors 0 to 11
bits : 2 - 2 (1 bit)

SNB : Sector number
bits : 3 - 7 (5 bit)

PSIZE : Program size
bits : 8 - 9 (2 bit)

MER1 : Mass Erase of sectors 12 to 23
bits : 15 - 15 (1 bit)

STRT : Start
bits : 16 - 16 (1 bit)

EOPIE : End of operation interrupt enable
bits : 24 - 24 (1 bit)

ERRIE : Error interrupt enable
bits : 25 - 25 (1 bit)

LOCK : Lock
bits : 31 - 31 (1 bit)


OPTCR

Flash option control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPTCR OPTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTLOCK OPTSTRT BOR_LEV WWDG_SW IWDG_SW nRST_STOP nRST_STDBY RDP nWRP IWDG_STDBY IWDG_STOP

OPTLOCK : Option lock
bits : 0 - 0 (1 bit)

OPTSTRT : Option start
bits : 1 - 1 (1 bit)

BOR_LEV : BOR reset Level
bits : 2 - 3 (2 bit)

WWDG_SW : User option bytes
bits : 4 - 4 (1 bit)

IWDG_SW : User option bytes
bits : 5 - 5 (1 bit)

nRST_STOP : User option bytes
bits : 6 - 6 (1 bit)

nRST_STDBY : User option bytes
bits : 7 - 7 (1 bit)

RDP : Read protect
bits : 8 - 15 (8 bit)

nWRP : Not write protect
bits : 16 - 23 (8 bit)

IWDG_STDBY : Independent watchdog counter freeze in standby mode
bits : 30 - 30 (1 bit)

IWDG_STOP : Independent watchdog counter freeze in Stop mode
bits : 31 - 31 (1 bit)


OPTCR1

Flash option control register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPTCR1 OPTCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOT_ADD0 BOOT_ADD1

BOOT_ADD0 : Boot base address when Boot pin =0
bits : 0 - 15 (16 bit)

BOOT_ADD1 : Boot base address when Boot pin =1
bits : 16 - 31 (16 bit)


KEYR

Flash key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYR KEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : FPEC key
bits : 0 - 31 (32 bit)


OPTKEYR

Flash option key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OPTKEYR OPTKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTKEY

OPTKEY : Option byte key
bits : 0 - 31 (32 bit)


SR

Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOP OPERR WRPERR PGAERR PGPERR PGSERR BSY

EOP : End of operation
bits : 0 - 0 (1 bit)
access : read-write

OPERR : Operation error
bits : 1 - 1 (1 bit)
access : read-write

WRPERR : Write protection error
bits : 4 - 4 (1 bit)
access : read-write

PGAERR : Programming alignment error
bits : 5 - 5 (1 bit)
access : read-write

PGPERR : Programming parallelism error
bits : 6 - 6 (1 bit)
access : read-write

PGSERR : Programming sequence error
bits : 7 - 7 (1 bit)
access : read-write

BSY : Busy
bits : 16 - 16 (1 bit)
access : read-only



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