DMA2D

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

CR

FGOR

BGMAR

BGOR

FGPFCCR

FGCOLR

BGPFCCR

BGCOLR

FGCMAR

BGCMAR

OPFCCR

OCOLR

OMAR

ISR

OOR

FGCLUT

NLR

LWR

AMTCR

IFCR

BGCLUT

FGMAR


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START SUSP ABORT TEIE TCIE TWIE CAEIE CTCIE CEIE MODE

START : Start
bits : 0 - 0 (1 bit)

SUSP : Suspend
bits : 1 - 1 (1 bit)

ABORT : Abort
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 8 - 8 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 9 - 9 (1 bit)

TWIE : Transfer watermark interrupt enable
bits : 10 - 10 (1 bit)

CAEIE : CLUT access error interrupt enable
bits : 11 - 11 (1 bit)

CTCIE : CLUT transfer complete interrupt enable
bits : 12 - 12 (1 bit)

CEIE : Configuration Error Interrupt Enable
bits : 13 - 13 (1 bit)

MODE : DMA2D mode
bits : 16 - 17 (2 bit)


FGOR

foreground offset register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FGOR FGOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LO

LO : Line offset
bits : 0 - 13 (14 bit)


BGMAR

background memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGMAR BGMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


BGOR

background offset register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGOR BGOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LO

LO : Line offset
bits : 0 - 13 (14 bit)


FGPFCCR

foreground PFC control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FGPFCCR FGPFCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM CCM START CS AM ALPHA

CM : Color mode
bits : 0 - 3 (4 bit)

CCM : CLUT color mode
bits : 4 - 4 (1 bit)

START : Start
bits : 5 - 5 (1 bit)

CS : CLUT size
bits : 8 - 15 (8 bit)

AM : Alpha mode
bits : 16 - 17 (2 bit)

ALPHA : Alpha value
bits : 24 - 31 (8 bit)


FGCOLR

foreground color register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FGCOLR FGCOLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED

BLUE : Blue Value
bits : 0 - 7 (8 bit)

GREEN : Green Value
bits : 8 - 15 (8 bit)

RED : Red Value
bits : 16 - 23 (8 bit)


BGPFCCR

background PFC control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGPFCCR BGPFCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM CCM START CS AM ALPHA

CM : Color mode
bits : 0 - 3 (4 bit)

CCM : CLUT Color mode
bits : 4 - 4 (1 bit)

START : Start
bits : 5 - 5 (1 bit)

CS : CLUT size
bits : 8 - 15 (8 bit)

AM : Alpha mode
bits : 16 - 17 (2 bit)

ALPHA : Alpha value
bits : 24 - 31 (8 bit)


BGCOLR

background color register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGCOLR BGCOLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED

BLUE : Blue Value
bits : 0 - 7 (8 bit)

GREEN : Green Value
bits : 8 - 15 (8 bit)

RED : Red Value
bits : 16 - 23 (8 bit)


FGCMAR

foreground CLUT memory address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FGCMAR FGCMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory Address
bits : 0 - 31 (32 bit)


BGCMAR

background CLUT memory address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGCMAR BGCMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


OPFCCR

output PFC control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPFCCR OPFCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM

CM : Color mode
bits : 0 - 2 (3 bit)


OCOLR

output color register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCOLR OCOLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED APLHA

BLUE : Blue Value
bits : 0 - 7 (8 bit)

GREEN : Green Value
bits : 8 - 15 (8 bit)

RED : Red Value
bits : 16 - 23 (8 bit)

APLHA : Alpha Channel Value
bits : 24 - 31 (8 bit)


OMAR

output memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMAR OMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory Address
bits : 0 - 31 (32 bit)


ISR

Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIF TCIF TWIF CAEIF CTCIF CEIF

TEIF : Transfer error interrupt flag
bits : 0 - 0 (1 bit)

TCIF : Transfer complete interrupt flag
bits : 1 - 1 (1 bit)

TWIF : Transfer watermark interrupt flag
bits : 2 - 2 (1 bit)

CAEIF : CLUT access error interrupt flag
bits : 3 - 3 (1 bit)

CTCIF : CLUT transfer complete interrupt flag
bits : 4 - 4 (1 bit)

CEIF : Configuration error interrupt flag
bits : 5 - 5 (1 bit)


OOR

output offset register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OOR OOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LO

LO : Line Offset
bits : 0 - 13 (14 bit)


FGCLUT

FGCLUT
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FGCLUT FGCLUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED APLHA

BLUE : BLUE
bits : 0 - 7 (8 bit)

GREEN : GREEN
bits : 8 - 15 (8 bit)

RED : RED
bits : 16 - 23 (8 bit)

APLHA : APLHA
bits : 24 - 31 (8 bit)


NLR

number of line register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NLR NLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NL PL

NL : Number of lines
bits : 0 - 15 (16 bit)

PL : Pixel per lines
bits : 16 - 29 (14 bit)


LWR

line watermark register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LWR LWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LW

LW : Line watermark
bits : 0 - 15 (16 bit)


AMTCR

AHB master timer configuration register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMTCR AMTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DT

EN : Enable
bits : 0 - 0 (1 bit)

DT : Dead Time
bits : 8 - 15 (8 bit)


IFCR

interrupt flag clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCR IFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEIF CTCIF CTWIF CAECIF CCTCIF CCEIF

CTEIF : Clear Transfer error interrupt flag
bits : 0 - 0 (1 bit)

CTCIF : Clear transfer complete interrupt flag
bits : 1 - 1 (1 bit)

CTWIF : Clear transfer watermark interrupt flag
bits : 2 - 2 (1 bit)

CAECIF : Clear CLUT access error interrupt flag
bits : 3 - 3 (1 bit)

CCTCIF : Clear CLUT transfer complete interrupt flag
bits : 4 - 4 (1 bit)

CCEIF : Clear configuration error interrupt flag
bits : 5 - 5 (1 bit)


BGCLUT

BGCLUT
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGCLUT BGCLUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED APLHA

BLUE : BLUE
bits : 0 - 7 (8 bit)

GREEN : GREEN
bits : 8 - 15 (8 bit)

RED : RED
bits : 16 - 23 (8 bit)

APLHA : APLHA
bits : 24 - 31 (8 bit)


FGMAR

foreground memory address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FGMAR FGMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)



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