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MPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x15 byte (0x0)
mem_usage : registers
protection :

Registers

MPU_TYPER (TYPER)

MPU_RASR (RASR)

MPU_CTRL (CTRL)

MPU_RNR (RNR)

MPU_RBAR (RBAR)


MPU_TYPER (TYPER)

MPU type register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MPU_TYPER MPU_TYPER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEPARATE DREGION IREGION

SEPARATE : Separate flag
bits : 0 - 0 (1 bit)

DREGION : Number of MPU data regions
bits : 8 - 15 (8 bit)

IREGION : Number of MPU instruction regions
bits : 16 - 23 (8 bit)


MPU_RASR (RASR)

MPU region attribute and size register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RASR MPU_RASR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region enable bit.
bits : 0 - 0 (1 bit)

SIZE : Size of the MPU protection region
bits : 1 - 5 (5 bit)

SRD : Subregion disable bits
bits : 8 - 15 (8 bit)

B : memory attribute
bits : 16 - 16 (1 bit)

C : memory attribute
bits : 17 - 17 (1 bit)

S : Shareable memory attribute
bits : 18 - 18 (1 bit)

TEX : memory attribute
bits : 19 - 21 (3 bit)

AP : Access permission
bits : 24 - 26 (3 bit)

XN : Instruction access disable bit
bits : 28 - 28 (1 bit)


MPU_CTRL (CTRL)

MPU control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MPU_CTRL MPU_CTRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE HFNMIENA PRIVDEFENA

ENABLE : Enables the MPU
bits : 0 - 0 (1 bit)

HFNMIENA : Enables the operation of MPU during hard fault
bits : 1 - 1 (1 bit)

PRIVDEFENA : Enable priviliged software access to default memory map
bits : 2 - 2 (1 bit)


MPU_RNR (RNR)

MPU region number register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RNR MPU_RNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION

REGION : MPU region
bits : 0 - 7 (8 bit)


MPU_RBAR (RBAR)

MPU region base address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RBAR MPU_RBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : MPU region field
bits : 0 - 3 (4 bit)

VALID : MPU region number valid
bits : 4 - 4 (1 bit)

ADDR : Region base address field
bits : 5 - 31 (27 bit)



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