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PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR1

CSR1

CR2

CSR2


CR1

power control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPDS PDDS CSBF PVDE PLS DBP FPDS LPUDS MRUDS ADCDC1 VOS ODEN ODSWEN UDEN

LPDS : Low-power deep sleep
bits : 0 - 0 (1 bit)

PDDS : Power down deepsleep
bits : 1 - 1 (1 bit)

CSBF : Clear standby flag
bits : 3 - 3 (1 bit)

PVDE : Power voltage detector enable
bits : 4 - 4 (1 bit)

PLS : PVD level selection
bits : 5 - 7 (3 bit)

DBP : Disable backup domain write protection
bits : 8 - 8 (1 bit)

FPDS : Flash power down in Stop mode
bits : 9 - 9 (1 bit)

LPUDS : Low-power regulator in deepsleep under-drive mode
bits : 10 - 10 (1 bit)

MRUDS : Main regulator in deepsleep under-drive mode
bits : 11 - 11 (1 bit)

ADCDC1 : ADCDC1
bits : 13 - 13 (1 bit)

VOS : Regulator voltage scaling output selection
bits : 14 - 15 (2 bit)

ODEN : Over-drive enable
bits : 16 - 16 (1 bit)

ODSWEN : Over-drive switching enabled
bits : 17 - 17 (1 bit)

UDEN : Under-drive enable in stop mode
bits : 18 - 19 (2 bit)


CSR1

power control/status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR1 CSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUIF SBF PVDO BRR BRE VOSRDY ODRDY ODSWRDY UDRDY

WUIF : Wakeup internal flag
bits : 0 - 0 (1 bit)
access : read-only

SBF : Standby flag
bits : 1 - 1 (1 bit)
access : read-only

PVDO : PVD output
bits : 2 - 2 (1 bit)
access : read-only

BRR : Backup regulator ready
bits : 3 - 3 (1 bit)
access : read-only

BRE : Backup regulator enable
bits : 9 - 9 (1 bit)
access : read-write

VOSRDY : Regulator voltage scaling output selection ready bit
bits : 14 - 14 (1 bit)
access : read-write

ODRDY : Over-drive mode ready
bits : 16 - 16 (1 bit)
access : read-write

ODSWRDY : Over-drive mode switching ready
bits : 17 - 17 (1 bit)
access : read-write

UDRDY : Under-drive ready flag
bits : 18 - 19 (2 bit)
access : read-write


CR2

power control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CWUPF1 CWUPF2 CWUPF3 CWUPF4 CWUPF5 CWUPF6 WUPP1 WUPP2 WUPP3 WUPP4 WUPP5 WUPP6

CWUPF1 : Clear Wakeup Pin flag for PA0
bits : 0 - 0 (1 bit)
access : read-only

CWUPF2 : Clear Wakeup Pin flag for PA2
bits : 1 - 1 (1 bit)
access : read-only

CWUPF3 : Clear Wakeup Pin flag for PC1
bits : 2 - 2 (1 bit)
access : read-only

CWUPF4 : Clear Wakeup Pin flag for PC13
bits : 3 - 3 (1 bit)
access : read-only

CWUPF5 : Clear Wakeup Pin flag for PI8
bits : 4 - 4 (1 bit)
access : read-only

CWUPF6 : Clear Wakeup Pin flag for PI11
bits : 5 - 5 (1 bit)
access : read-only

WUPP1 : Wakeup pin polarity bit for PA0
bits : 8 - 8 (1 bit)
access : read-write

WUPP2 : Wakeup pin polarity bit for PA2
bits : 9 - 9 (1 bit)
access : read-write

WUPP3 : Wakeup pin polarity bit for PC1
bits : 10 - 10 (1 bit)
access : read-write

WUPP4 : Wakeup pin polarity bit for PC13
bits : 11 - 11 (1 bit)
access : read-write

WUPP5 : Wakeup pin polarity bit for PI8
bits : 12 - 12 (1 bit)
access : read-write

WUPP6 : Wakeup pin polarity bit for PI11
bits : 13 - 13 (1 bit)
access : read-write


CSR2

power control/status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR2 CSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUPF1 WUPF2 WUPF3 WUPF4 WUPF5 WUPF6 EWUP1 EWUP2 EWUP3 EWUP4 EWUP5 EWUP6

WUPF1 : Wakeup Pin flag for PA0
bits : 0 - 0 (1 bit)
access : read-only

WUPF2 : Wakeup Pin flag for PA2
bits : 1 - 1 (1 bit)
access : read-only

WUPF3 : Wakeup Pin flag for PC1
bits : 2 - 2 (1 bit)
access : read-only

WUPF4 : Wakeup Pin flag for PC13
bits : 3 - 3 (1 bit)
access : read-only

WUPF5 : Wakeup Pin flag for PI8
bits : 4 - 4 (1 bit)
access : read-only

WUPF6 : Wakeup Pin flag for PI11
bits : 5 - 5 (1 bit)
access : read-only

EWUP1 : Enable Wakeup pin for PA0
bits : 8 - 8 (1 bit)
access : read-write

EWUP2 : Enable Wakeup pin for PA2
bits : 9 - 9 (1 bit)
access : read-write

EWUP3 : Enable Wakeup pin for PC1
bits : 10 - 10 (1 bit)
access : read-write

EWUP4 : Enable Wakeup pin for PC13
bits : 11 - 11 (1 bit)
access : read-write

EWUP5 : Enable Wakeup pin for PI8
bits : 12 - 12 (1 bit)
access : read-write

EWUP6 : Enable Wakeup pin for PI11
bits : 13 - 13 (1 bit)
access : read-write



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