Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDY : ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
ADC is ready to start conversion
End of enumeration elements list.
EOSMP : End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
End of sampling phase reached
End of enumeration elements list.
EOC : End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Regular channel conversion complete
End of enumeration elements list.
EOS : End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Regular Conversions sequence complete
End of enumeration elements list.
OVR : ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No overrun occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Overrun has occurred
End of enumeration elements list.
JEOC : Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Injected channel conversion complete
End of enumeration elements list.
JEOS : Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Injected conversions complete
End of enumeration elements list.
AWD1 : Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog 1 event occurred
End of enumeration elements list.
AWD2 : Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog 2 event occurred
End of enumeration elements list.
AWD3 : Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog 3 event occurred
End of enumeration elements list.
JQOVF : Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Injected context queue overflow has occurred
End of enumeration elements list.
LDORDY : ADC LDO output voltage ready bit This bit is set and cleared by hardware. It indicates that the ADC internal LDO output is ready and that the ADC can be enabled or calibrated. Note: Refer to for the availability of the LDO regulator.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
ADC LDO voltage regulator disabled
0x1 : B_0x1
ADC LDO voltage regulator enabled
End of enumeration elements list.
ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROVSE : Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular Oversampling disabled
0x1 : B_0x1
Regular Oversampling enabled
End of enumeration elements list.
JOVSE : Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected Oversampling disabled
0x1 : B_0x1
Injected Oversampling enabled
End of enumeration elements list.
OVSS : Oversampling right shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No right shift
0x1 : B_0x1
Shift right 1-bit
0x2 : B_0x2
Shift right 2-bits
0x3 : B_0x3
Shift right 3-bits
0x4 : B_0x4
Shift right 4-bits
0x5 : B_0x5
Shift right 5-bits
0x6 : B_0x6
Shift right 6-bits
0x7 : B_0x7
Shift right 7-bits
0x8 : B_0x8
Shift right 8-bits
0x9 : B_0x9
Shift right 9-bits
0xA : B_0xA
Shift right 10-bits
0xB : B_0xB
Shift right 11-bits
End of enumeration elements list.
TROVS : Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
All oversampled conversions for a channel are done consecutively following a trigger
0x1 : B_0x1
Each oversampled conversion for a channel needs a new trigger
End of enumeration elements list.
ROVSM : Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
0x1 : B_0x1
Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
End of enumeration elements list.
RSHIFT1 : Right-shift data after Offset 1 correction This bitfield is set and cleared by software to right-shift 1-bit data after offset1 correction. This bit can only be used for 8-bit and 16-bit data format (see (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right-shifting disabled
0x1 : B_0x1
Data is right-shifted 1-bit.
End of enumeration elements list.
RSHIFT2 : Right-shift data after Offset 2 correction Refer to RSHIFT1 description
bits : 12 - 12 (1 bit)
access : read-write
RSHIFT3 : Right-shift data after Offset 3 correction Refer to RSHIFT1 description
bits : 13 - 13 (1 bit)
access : read-write
RSHIFT4 : Right-shift data after Offset 4 correction Refer to RSHIFT1 description.
bits : 14 - 14 (1 bit)
access : read-write
OSVR : Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2: 3x ... 1023: 1024x Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 16 - 25 (10 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1x (no oversampling)
0x1 : B_0x1
2x
End of enumeration elements list.
LSHIFT : Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No left shift
0x1 : B_0x1
Shift left 1-bit
0x2 : B_0x2
Shift left 2-bits
0x3 : B_0x3
Shift left 3-bits
0x4 : B_0x4
Shift left 4-bits
0x5 : B_0x5
Shift left 5-bits
0x6 : B_0x6
Shift left 6-bits
0x7 : B_0x7
Shift left 7-bits
0x8 : B_0x8
Shift left 8-bits
0x9 : B_0x9
Shift left 9-bits
0xA : B_0xA
Shift left 10-bits
0xB : B_0xB
Shift left 11-bits
0xC : B_0xC
Shift left 12-bits
0xD : B_0xD
Shift left 13-bits
0xE : B_0xE
Shift left 14-bits
0xF : B_0xF
Shift left 15-bits
End of enumeration elements list.
ADC sample time register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP0 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP1 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP2 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP3 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP4 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP5 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP6 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP7 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP8 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP9 : Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
ADC sample time register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP10 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP11 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP12 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP13 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP14 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP15 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP16 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP17 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP18 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
SMP19 : Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
2.5 ADC clock cycles
0x2 : B_0x2
8.5 ADC clock cycles
0x3 : B_0x3
16.5 ADC clock cycles
0x4 : B_0x4
32.5 ADC clock cycles
0x5 : B_0x5
64.5 ADC clock cycles
0x6 : B_0x6
387.5 ADC clock cycles
0x7 : B_0x7
810.5 ADC clock cycles
End of enumeration elements list.
ADC channel preselection register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCSEL0 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL1 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL2 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL3 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL4 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL5 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL6 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL7 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL8 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL9 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL10 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL11 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL12 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL13 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL14 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL15 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL16 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL17 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL18 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
PCSEL19 : :Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result.
0x1 : B_0x1
Input Channel x (Vinp x) is pre selected for conversion
End of enumeration elements list.
ADC watchdog threshold register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTR1 : Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 25 (26 bit)
access : read-write
ADC watchdog threshold register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTR1 : Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 25 (26 bit)
access : read-write
ADC regular sequence register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L : Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 conversion
0x1 : B_0x1
2 conversions
0xF : B_0xF
16 conversions
End of enumeration elements list.
SQ1 : 1st conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
SQ2 : 2nd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 12 - 16 (5 bit)
access : read-write
SQ3 : 3rd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 18 - 22 (5 bit)
access : read-write
SQ4 : 4th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the regular conversion sequence.
bits : 24 - 28 (5 bit)
access : read-write
ADC regular sequence register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ5 : 5th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 5th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 0 - 4 (5 bit)
access : read-write
SQ6 : 6th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
SQ7 : 7th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 7th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 12 - 16 (5 bit)
access : read-write
SQ8 : 8th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 18 - 22 (5 bit)
access : read-write
SQ9 : 9th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 24 - 28 (5 bit)
access : read-write
ADC regular sequence register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ10 : 10th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 10th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 0 - 4 (5 bit)
access : read-write
SQ11 : 11th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
SQ12 : 12th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 12th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 12 - 16 (5 bit)
access : read-write
SQ13 : 13th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 18 - 22 (5 bit)
access : read-write
SQ14 : 14th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 24 - 28 (5 bit)
access : read-write
ADC regular sequence register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ15 : 15th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 15th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 0 - 4 (5 bit)
access : read-write
SQ16 : 16th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDYIE : ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADRDY interrupt disabled
0x1 : B_0x1
ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
End of enumeration elements list.
EOSMPIE : End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOSMP interrupt disabled.
0x1 : B_0x1
EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
End of enumeration elements list.
EOCIE : End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOC interrupt disabled.
0x1 : B_0x1
EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
End of enumeration elements list.
EOSIE : End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOS interrupt disabled
0x1 : B_0x1
EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
End of enumeration elements list.
OVRIE : Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Overrun interrupt disabled
0x1 : B_0x1
Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
End of enumeration elements list.
JEOCIE : End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART is cleared to 0 (no injected conversion is ongoing).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
JEOC interrupt disabled.
0x1 : B_0x1
JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
End of enumeration elements list.
JEOSIE : End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
JEOS interrupt disabled
0x1 : B_0x1
JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
End of enumeration elements list.
AWD1IE : Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 interrupt disabled
0x1 : B_0x1
Analog watchdog 1 interrupt enabled
End of enumeration elements list.
AWD2IE : Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 2 interrupt disabled
0x1 : B_0x1
Analog watchdog 2 interrupt enabled
End of enumeration elements list.
AWD3IE : Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 3 interrupt disabled
0x1 : B_0x1
Analog watchdog 3 interrupt enabled
End of enumeration elements list.
JQOVFIE : Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected Context Queue Overflow interrupt disabled
0x1 : B_0x1
Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set.
End of enumeration elements list.
ADC regular Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATA : Regular Data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in .
bits : 0 - 31 (32 bit)
access : read-only
ADC injected sequence register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JL : Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 conversion
0x1 : B_0x1
2 conversions
0x2 : B_0x2
3 conversions
0x3 : B_0x3
4 conversions
End of enumeration elements list.
JEXTSEL : External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing).
bits : 2 - 6 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Event 0
0x1 : B_0x1
Event 1
0x2 : B_0x2
Event 2
0x3 : B_0x3
Event 3
0x4 : B_0x4
Event 4
0x5 : B_0x5
Event 5
0x6 : B_0x6
Event 6
0x7 : B_0x7
Event 7
0x1F : B_0x1F
Event 31:
End of enumeration elements list.
JEXTEN : External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing). If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions)
bits : 7 - 8 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled and
0x1 : B_0x1
Hardware trigger detection on the rising edge
0x2 : B_0x2
Hardware trigger detection on the falling edge
0x3 : B_0x3
Hardware trigger detection on both the rising and falling edges
End of enumeration elements list.
JSQ1 : 1st conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register).
bits : 9 - 13 (5 bit)
access : read-write
JSQ2 : 2nd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register).
bits : 15 - 19 (5 bit)
access : read-write
JSQ3 : 3rd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register).
bits : 21 - 25 (5 bit)
access : read-write
JSQ4 : 4th conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register).
bits : 27 - 31 (5 bit)
access : read-write
ADC injected channel 1 offset register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET1 : Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4.
bits : 0 - 25 (26 bit)
access : read-write
OFFSET1_CH : Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 26 - 30 (5 bit)
access : read-write
SSATE : Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format).
0x1 : B_0x1
Offset is subtracted and result is saturated to maintain result size.
End of enumeration elements list.
ADC injected channel 2 offset register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET2 : Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4.
bits : 0 - 25 (26 bit)
access : read-write
OFFSET2_CH : Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 26 - 30 (5 bit)
access : read-write
SSATE : Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format).
0x1 : B_0x1
Offset is subtracted and result is saturated to maintain result size.
End of enumeration elements list.
ADC injected channel 3 offset register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET3 : Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4.
bits : 0 - 25 (26 bit)
access : read-write
OFFSET3_CH : Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 26 - 30 (5 bit)
access : read-write
SSATE : Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format).
0x1 : B_0x1
Offset is subtracted and result is saturated to maintain result size.
End of enumeration elements list.
ADC injected channel 4 offset register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET4 : Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4.
bits : 0 - 25 (26 bit)
access : read-write
OFFSET4_CH : Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 26 - 30 (5 bit)
access : read-write
SSATE : Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format).
0x1 : B_0x1
Offset is subtracted and result is saturated to maintain result size.
End of enumeration elements list.
ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : ADC enable control This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC is disabled (OFF state)
0x1 : B_0x1
Write 1 to enable the ADC.
End of enumeration elements list.
ADDIS : ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no ADDIS command ongoing
0x1 : B_0x1
Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
End of enumeration elements list.
ADSTART : ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode (CONT=0, DISCEN=0) when software trigger is selected (EXTEN=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. In discontinuous conversion mode (CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=0x0): at the end of conversion (EOC) flag. in all other cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC regular conversion is ongoing.
0x1 : B_0x1
Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel.
End of enumeration elements list.
JADSTART : ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC injected conversion is ongoing.
0x1 : B_0x1
Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel.
End of enumeration elements list.
ADSTP : ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the master ADC must be used to stop regular conversions. The other ADSTP bit is inactive.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC stop regular conversion command ongoing
0x1 : B_0x1
Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress.
End of enumeration elements list.
JADSTP : ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC stop injected conversion command ongoing
0x1 : B_0x1
Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress.
End of enumeration elements list.
BOOST : Boost mode control This bitfield is set and cleared by software to enable/disable the Boost mode. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the BOOST bitfield of the slave ADC is no more writable and its content must be equal to the master ADC BOOST bitfield.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
used when ADC clock ≤ 6.25 MHz
0x1 : B_0x1
used when 6.25 MHz < ADC clock frequency≤ 12.5 MHz
0x2 : B_0x2
used when 12.5 MHz < ADC clock ≤25.0 MHz
0x3 : B_0x3
used when 25.0 MHz < ADC clock ≤ 50.0 MHz
End of enumeration elements list.
ADCALLIN : Linearity calibration This bit is set and cleared by software to enable the Linearity calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing ADCAL will launch a calibration without the Linearity calibration.
0x1 : B_0x1
Writing ADCAL will launch a calibration with he Linearity calibration.
End of enumeration elements list.
LINCALRDYW1 : Linearity calibration ready Word 1 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[29:0]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW2 bits are left unchanged.
bits : 22 - 22 (1 bit)
access : read-write
LINCALRDYW2 : Linearity calibration ready Word 2 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[59:30]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW1 bits are left unchanged.
bits : 23 - 23 (1 bit)
access : read-write
LINCALRDYW3 : Linearity calibration ready Word 3 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[89:60]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
bits : 24 - 24 (1 bit)
access : read-write
LINCALRDYW4 : Linearity calibration ready Word 4 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] correspond linearity correction factor bits[119:90]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
bits : 25 - 25 (1 bit)
access : read-write
LINCALRDYW5 : Linearity calibration ready Word 5 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[149:120]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
bits : 26 - 26 (1 bit)
access : read-write
LINCALRDYW6 : Linearity calibration ready Word 6 This control / status bit allows to read/write the 6th linearity calibration factor. When the linearity calibration is complete, this bit is set. A bit clear will launch the transfer of the linearity factor 6 into the LINCALFACT[29:0] of the ADC_CALFACT2 register. The bit will be reset by hardware when the ADC_CALFACT2 register can be read (software must poll the bit until it is cleared). When the LINCALRDYW6 bit is reset, a new linearity factor 6 value can be written into the LINCALFACT[29:0] of the ADC_CALFACT2 register. A bit set will launch the linearity factor 6 update and the bit will be effectively set by hardware once the update will be done (software must poll the bit until it is set to indicate the write is effective). Note: ADC_CALFACT2[29:10] contains 0. ADC_CALFACT2[9:0] corresponds linearity correction factor bits[159:150]. The software is allowed to toggle this bit only if the LINCALRDYW5, LINCALRDYW4, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged, see chapter for details. The software is allowed to update the linearity calibration factor by writing LINCALRDYWx only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)
bits : 27 - 27 (1 bit)
access : read-write
ADVREGEN : ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bitfield only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC Voltage regulator disabled
0x1 : B_0x1
ADC Voltage regulator enabled.
End of enumeration elements list.
DEEPPWD : Deep-power-down enable This bit is set and cleared by software to put the ADC in deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC not in deep-power down
0x1 : B_0x1
ADC in deep-power-down (default reset state)
End of enumeration elements list.
ADCALDIF : Differential mode for calibration This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing ADCAL will launch a calibration in Single-ended inputs Mode.
0x1 : B_0x1
Writing ADCAL will launch a calibration in Differential inputs Mode.
End of enumeration elements list.
ADCAL : ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Calibration complete
0x1 : B_0x1
Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
End of enumeration elements list.
ADC injected channel 1 data register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 31 (32 bit)
access : read-only
ADC injected channel 2 data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 31 (32 bit)
access : read-only
ADC injected channel 3 data register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 31 (32 bit)
access : read-only
ADC injected channel 4 data register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 31 (32 bit)
access : read-only
ADC analog watchdog 2 configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD2CH : Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 19 (20 bit)
access : read-write
ADC analog watchdog 3 configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD3CH : Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 19 (20 bit)
access : read-write
ADC watchdog lower threshold register 2
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTR2 : Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 25 (26 bit)
access : read-write
ADC watchdog higher threshold register 2
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTR2 : Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 25 (26 bit)
access : read-write
ADC watchdog lower threshold register 3
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTR3 : Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 25 (26 bit)
access : read-write
ADC watchdog higher threshold register 3
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTR3 : Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 25 (26 bit)
access : read-write
ADC configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMNGT : Data Management configuration This bit is set and cleared by software to select how ADC interface output data are managed. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). In dual-ADC modes, this bit is not relevant and replaced by control bit DAMDF of the ADCx_CCR register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular conversion data stored in DR only
0x1 : B_0x1
DMA One Shot Mode selected
0x2 : B_0x2
DFSDM mode selected
0x3 : B_0x3
DMA Circular Mode selected
End of enumeration elements list.
RES : Data resolution These bits are written by software to select the resolution of the conversion. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
16 bits
0x1 : B_0x1
14 bits in legacy mode (not optimized power consumption)
0x2 : B_0x2
12 bits in legacy mode (not optimized power consumption)
0x5 : B_0x5
14 bits
0x6 : B_0x6
12 bits
0x3 : B_0x3
10 bits
0x7 : B_0x7
8 bits
End of enumeration elements list.
EXTSEL : External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Event 0
0x1 : B_0x1
Event 1
0x2 : B_0x2
Event 2
0x3 : B_0x3
Event 3
0x4 : B_0x4
Event 4
0x5 : B_0x5
Event 5
0x6 : B_0x6
Event 6
0x7 : B_0x7
Event 7
0x1F : B_0x1F
Event 31
End of enumeration elements list.
EXTEN : External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Hardware trigger detection disabled (conversions can be launched by software)
0x1 : B_0x1
Hardware trigger detection on the rising edge
0x2 : B_0x2
Hardware trigger detection on the falling edge
0x3 : B_0x3
Hardware trigger detection on both the rising and falling edges
End of enumeration elements list.
OVRMOD : Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC_DR register is preserved with the old data when an overrun is detected.
0x1 : B_0x1
ADC_DR register is overwritten with the last conversion result when an overrun is detected.
End of enumeration elements list.
CONT : Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Single conversion mode
0x1 : B_0x1
Continuous conversion mode
End of enumeration elements list.
AUTDLY : Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Auto-delayed conversion mode off
0x1 : B_0x1
Auto-delayed conversion mode on
End of enumeration elements list.
DISCEN : Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Discontinuous mode for regular channels disabled
0x1 : B_0x1
Discontinuous mode for regular channels enabled
End of enumeration elements list.
DISCNUM : Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC.
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 channel
0x1 : B_0x1
2 channels
0x7 : B_0x7
8 channels
End of enumeration elements list.
JDISCEN : Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Discontinuous mode on injected channels disabled
0x1 : B_0x1
Discontinuous mode on injected channels enabled
End of enumeration elements list.
JQM : JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
JSQR Mode 0: The Queue is never empty and maintains the last written configuration into JSQR.
0x1 : B_0x1
JSQR Mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence.
End of enumeration elements list.
AWD1SGL : Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 enabled on all channels
0x1 : B_0x1
Analog watchdog 1 enabled on a single channel
End of enumeration elements list.
AWD1EN : Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 disabled on regular channels
0x1 : B_0x1
Analog watchdog 1 enabled on regular channels
End of enumeration elements list.
JAWD1EN : Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 disabled on injected channels
0x1 : B_0x1
Analog watchdog 1 enabled on injected channels
End of enumeration elements list.
JAUTO : Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Automatic injected group conversion disabled
0x1 : B_0x1
Automatic injected group conversion enabled
End of enumeration elements list.
AWD1CH : Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: Reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
bits : 26 - 30 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog input channel-0 monitored by AWD1
0x1 : B_0x1
ADC analog input channel-1 monitored by AWD1
0x12 : B_0x12
ADC analog input channel-19 monitored by AWD1
End of enumeration elements list.
JQDIS : Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism: Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected Queue enabled
0x1 : B_0x1
Injected Queue disabled
End of enumeration elements list.
ADC differential mode selection register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFSEL : Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow to select if a channel is configured as single ended or differential mode. DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
bits : 0 - 19 (20 bit)
access : read-write
ADC calibration factors register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALFACT_S : Calibration Factors In Single-Ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended conversion is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).
bits : 0 - 10 (11 bit)
access : read-write
CALFACT_D : Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential conversion is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).
bits : 16 - 26 (11 bit)
access : read-write
ADC calibration factor register 2
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINCALFACT : Linearity Calibration Factor These bits are written by hardware or by software. They hold 30-bit out of the 160-bit linearity calibration factor. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).
bits : 0 - 29 (30 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.