Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDY : ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
ADC is ready to start conversion
End of enumeration elements list.
EOSMP : End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
End of sampling phase reached
End of enumeration elements list.
EOC : End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Regular channel conversion complete
End of enumeration elements list.
EOS : End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Regular Conversions sequence complete
End of enumeration elements list.
OVR : ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No overrun occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Overrun has occurred
End of enumeration elements list.
JEOC : Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Injected channel conversion complete
End of enumeration elements list.
JEOS : Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Injected conversions complete
End of enumeration elements list.
AWD1 : Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog 1 event occurred
End of enumeration elements list.
AWD2 : Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog 2 event occurred
End of enumeration elements list.
AWD3 : Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog 3 event occurred
End of enumeration elements list.
JQOVF : Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Injected context queue overflow has occurred
End of enumeration elements list.
ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROVSE : Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular Oversampling disabled
0x1 : B_0x1
Regular Oversampling enabled
End of enumeration elements list.
JOVSE : Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected Oversampling disabled
0x1 : B_0x1
Injected Oversampling enabled
End of enumeration elements list.
OVSR : Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2x
0x1 : B_0x1
4x
0x2 : B_0x2
8x
0x3 : B_0x3
16x
0x4 : B_0x4
32x
0x5 : B_0x5
64x
0x6 : B_0x6
128x
0x7 : B_0x7
256x
End of enumeration elements list.
OVSS : Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No shift
0x1 : B_0x1
Shift 1-bit
0x2 : B_0x2
Shift 2-bits
0x3 : B_0x3
Shift 3-bits
0x4 : B_0x4
Shift 4-bits
0x5 : B_0x5
Shift 5-bits
0x6 : B_0x6
Shift 6-bits
0x7 : B_0x7
Shift 7-bits
0x8 : B_0x8
Shift 8-bits
End of enumeration elements list.
TROVS : Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
All oversampled conversions for a channel are done consecutively following a trigger
0x1 : B_0x1
Each oversampled conversion for a channel needs a new trigger
End of enumeration elements list.
ROVSM : Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
0x1 : B_0x1
Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
End of enumeration elements list.
SWTRIG : Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Software trigger starts the conversion for sampling time control trigger mode
0x1 : B_0x1
Software trigger starts the sampling for sampling time control trigger mode
End of enumeration elements list.
BULB : Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bulb sampling mode disabled
0x1 : B_0x1
Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion.
End of enumeration elements list.
SMPTRIG : Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time control trigger mode disabled
0x1 : B_0x1
Sampling time control trigger mode enabled
End of enumeration elements list.
ADC sample time register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP0 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP1 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP2 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP3 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP4 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP5 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP6 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP7 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP8 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP9 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMPPLUS : Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x1 : B_0x1
2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers.
0x0 : B_0x0
The sampling time remains set to 2.5 ADC clock cycles remains
End of enumeration elements list.
ADC sample time register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP10 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP11 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP12 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP13 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP14 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP15 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP16 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP17 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
SMP18 : Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2.5 ADC clock cycles
0x1 : B_0x1
6.5 ADC clock cycles
0x2 : B_0x2
12.5 ADC clock cycles
0x3 : B_0x3
24.5 ADC clock cycles
0x4 : B_0x4
47.5 ADC clock cycles
0x5 : B_0x5
92.5 ADC clock cycles
0x6 : B_0x6
247.5 ADC clock cycles
0x7 : B_0x7
640.5 ADC clock cycles
End of enumeration elements list.
ADC watchdog threshold register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT1 : Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 0 - 11 (12 bit)
access : read-write
AWDFILT : Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No filtering
0x1 : B_0x1
two consecutive detection generates an AWDx flag or an interrupt
0x7 : B_0x7
Eight consecutive detection generates an AWDx flag or an interrupt
End of enumeration elements list.
HT1 : Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 16 - 27 (12 bit)
access : read-write
ADC watchdog threshold register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT2 : Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 0 - 7 (8 bit)
access : read-write
HT2 : Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 16 - 23 (8 bit)
access : read-write
ADC watchdog threshold register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT3 : Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 0 - 7 (8 bit)
access : read-write
HT3 : Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 16 - 23 (8 bit)
access : read-write
ADC regular sequence register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L : Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 conversion
0x1 : B_0x1
2 conversions
0xF : B_0xF
16 conversions
End of enumeration elements list.
SQ1 : 1st conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
SQ2 : 2nd conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 12 - 16 (5 bit)
access : read-write
SQ3 : 3rd conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 18 - 22 (5 bit)
access : read-write
SQ4 : 4th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 24 - 28 (5 bit)
access : read-write
ADC regular sequence register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ5 : 5th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 5th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 0 - 4 (5 bit)
access : read-write
SQ6 : 6th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
SQ7 : 7th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 7th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 12 - 16 (5 bit)
access : read-write
SQ8 : 8th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 18 - 22 (5 bit)
access : read-write
SQ9 : 9th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 24 - 28 (5 bit)
access : read-write
ADC regular sequence register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ10 : 10th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 10th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 0 - 4 (5 bit)
access : read-write
SQ11 : 11th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
SQ12 : 12th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 12th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 12 - 16 (5 bit)
access : read-write
SQ13 : 13th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 18 - 22 (5 bit)
access : read-write
SQ14 : 14th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 24 - 28 (5 bit)
access : read-write
ADC regular sequence register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ15 : 15th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 15th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 0 - 4 (5 bit)
access : read-write
SQ16 : 16th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 6 - 10 (5 bit)
access : read-write
ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDYIE : ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADRDY interrupt disabled
0x1 : B_0x1
ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
End of enumeration elements list.
EOSMPIE : End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOSMP interrupt disabled.
0x1 : B_0x1
EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
End of enumeration elements list.
EOCIE : End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOC interrupt disabled.
0x1 : B_0x1
EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
End of enumeration elements list.
EOSIE : End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOS interrupt disabled
0x1 : B_0x1
EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
End of enumeration elements list.
OVRIE : Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Overrun interrupt disabled
0x1 : B_0x1
Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
End of enumeration elements list.
JEOCIE : End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
JEOC interrupt disabled.
0x1 : B_0x1
JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
End of enumeration elements list.
JEOSIE : End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
JEOS interrupt disabled
0x1 : B_0x1
JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
End of enumeration elements list.
AWD1IE : Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 interrupt disabled
0x1 : B_0x1
Analog watchdog 1 interrupt enabled
End of enumeration elements list.
AWD2IE : Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 2 interrupt disabled
0x1 : B_0x1
Analog watchdog 2 interrupt enabled
End of enumeration elements list.
AWD3IE : Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 3 interrupt disabled
0x1 : B_0x1
Analog watchdog 3 interrupt enabled
End of enumeration elements list.
JQOVFIE : Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected Context Queue Overflow interrupt disabled
0x1 : B_0x1
Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set.
End of enumeration elements list.
ADC regular data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATA : Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in .
bits : 0 - 15 (16 bit)
access : read-only
ADC injected sequence register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JL : Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 conversion
0x1 : B_0x1
2 conversions
0x2 : B_0x2
3 conversions
0x3 : B_0x3
4 conversions
End of enumeration elements list.
JEXTSEL : External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 2 - 6 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
adc_jext_trg0
0x1 : B_0x1
adc_jext_trg1
0x2 : B_0x2
adc_jext_trg2
0x3 : B_0x3
adc_jext_trg3
0x4 : B_0x4
adc_jext_trg4
0x5 : B_0x5
adc_jext_trg5
0x6 : B_0x6
adc_jext_trg6
0x7 : B_0x7
adc_jext_trg7
0x1F : B_0x1F
adc_jext_trg31
End of enumeration elements list.
JEXTEN : External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions)
bits : 7 - 8 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
If JQDIS = 0 (queue enabled), hardware and software trigger detection disabled. Otherwise, the queue is disabled as well as hardware trigger detection (conversions can be launched by software)
0x1 : B_0x1
Hardware trigger detection on the rising edge
0x2 : B_0x2
Hardware trigger detection on the falling edge
0x3 : B_0x3
Hardware trigger detection on both the rising and falling edges
End of enumeration elements list.
JSQ1 : 1st conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 9 - 13 (5 bit)
access : read-write
JSQ2 : 2nd conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 15 - 19 (5 bit)
access : read-write
JSQ3 : 3rd conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 21 - 25 (5 bit)
access : read-write
JSQ4 : 4th conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 27 - 31 (5 bit)
access : read-write
ADC offset 1 register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4.
bits : 0 - 11 (12 bit)
access : read-write
OFFSETPOS : Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Negative offset
0x1 : B_0x1
Positive offset
End of enumeration elements list.
SATEN : Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No saturation control, offset result can be signed
0x1 : B_0x1
Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF
End of enumeration elements list.
OFFSET_CH : Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers.
bits : 26 - 30 (5 bit)
access : read-write
OFFSET_EN : Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
ADC offset 2 register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4.
bits : 0 - 11 (12 bit)
access : read-write
OFFSETPOS : Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Negative offset
0x1 : B_0x1
Positive offset
End of enumeration elements list.
SATEN : Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No saturation control, offset result can be signed
0x1 : B_0x1
Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF
End of enumeration elements list.
OFFSET_CH : Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers.
bits : 26 - 30 (5 bit)
access : read-write
OFFSET_EN : Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
ADC offset 3 register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4.
bits : 0 - 11 (12 bit)
access : read-write
OFFSETPOS : Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Negative offset
0x1 : B_0x1
Positive offset
End of enumeration elements list.
SATEN : Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No saturation control, offset result can be signed
0x1 : B_0x1
Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF
End of enumeration elements list.
OFFSET_CH : Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers.
bits : 26 - 30 (5 bit)
access : read-write
OFFSET_EN : Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
ADC offset 4 register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4.
bits : 0 - 11 (12 bit)
access : read-write
OFFSETPOS : Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Negative offset
0x1 : B_0x1
Positive offset
End of enumeration elements list.
SATEN : Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No saturation control, offset result can be signed
0x1 : B_0x1
Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF
End of enumeration elements list.
OFFSET_CH : Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers.
bits : 26 - 30 (5 bit)
access : read-write
OFFSET_EN : Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC is disabled (OFF state)
0x1 : B_0x1
Write 1 to enable the ADC.
End of enumeration elements list.
ADDIS : ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no ADDIS command ongoing
0x1 : B_0x1
Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
End of enumeration elements list.
ADSTART : ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC regular conversion is ongoing.
0x1 : B_0x1
Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel.
End of enumeration elements list.
JADSTART : ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC injected conversion is ongoing.
0x1 : B_0x1
Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel.
End of enumeration elements list.
ADSTP : ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC stop regular conversion command ongoing
0x1 : B_0x1
Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress.
End of enumeration elements list.
JADSTP : ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC stop injected conversion command ongoing
0x1 : B_0x1
Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress.
End of enumeration elements list.
ADVREGEN : ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC Voltage regulator disabled
0x1 : B_0x1
ADC Voltage regulator enabled.
End of enumeration elements list.
DEEPPWD : Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC not in Deep-power down
0x1 : B_0x1
ADC in Deep-power-down (default reset state)
End of enumeration elements list.
ADCALDIF : Differential mode for calibration This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing ADCAL launches a calibration in Single-ended inputs mode.
0x1 : B_0x1
Writing ADCAL launches a calibration in Differential inputs mode.
End of enumeration elements list.
ADCAL : ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Calibration complete
0x1 : B_0x1
Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
End of enumeration elements list.
ADC injected channel 1 data register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 15 (16 bit)
access : read-only
ADC injected channel 2 data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 15 (16 bit)
access : read-only
ADC injected channel 3 data register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 15 (16 bit)
access : read-only
ADC injected channel 4 data register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in .
bits : 0 - 15 (16 bit)
access : read-only
ADC Analog Watchdog 2 Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD2CH : Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog.
bits : 0 - 18 (19 bit)
access : read-write
ADC Analog Watchdog 3 Configuration Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD3CH : Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog.
bits : 0 - 18 (19 bit)
access : read-write
ADC Differential mode Selection Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFSEL : Differential mode for channels 18 to 0. These bits are set and cleared by software. They allow to select if a channel is configured as Single-ended or Differential mode. DIFSEL[i] = 0: ADC analog input channel is configured in Single-ended mode DIFSEL[i] = 1: ADC analog input channel i is configured in Differential mode Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (Single-ended input mode). The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
bits : 0 - 18 (19 bit)
access : read-write
ADC Calibration Factors
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALFACT_S : Calibration Factors In Single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).
bits : 0 - 6 (7 bit)
access : read-write
CALFACT_D : Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).
bits : 16 - 22 (7 bit)
access : read-write
ADC configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA disabled
0x1 : B_0x1
DMA enabled
End of enumeration elements list.
DMACFG : Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA One Shot mode selected
0x1 : B_0x1
DMA Circular mode selected
End of enumeration elements list.
DFSDMCFG : DFSDM mode configuration This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN = 0. Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM mode disabled
0x1 : B_0x1
DFSDM mode enabled
End of enumeration elements list.
RES : Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
12-bit
0x1 : B_0x1
10-bit
0x2 : B_0x2
8-bit
0x3 : B_0x3
6-bit
End of enumeration elements list.
EXTSEL0 : External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
adc_ext_trg0
0x1 : B_0x1
adc_ext_trg1
0x2 : B_0x2
adc_ext_trg2
0x3 : B_0x3
adc_ext_trg3
0x4 : B_0x4
adc_ext_trg4
0x5 : B_0x5
adc_ext_trg5
0x6 : B_0x6
adc_ext_trg6
0x7 : B_0x7
adc_ext_trg7
0x1F : B_0x1F
adc_ext_trg31
End of enumeration elements list.
EXTSEL1 : External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
adc_ext_trg0
0x1 : B_0x1
adc_ext_trg1
0x2 : B_0x2
adc_ext_trg2
0x3 : B_0x3
adc_ext_trg3
0x4 : B_0x4
adc_ext_trg4
0x5 : B_0x5
adc_ext_trg5
0x6 : B_0x6
adc_ext_trg6
0x7 : B_0x7
adc_ext_trg7
0x1F : B_0x1F
adc_ext_trg31
End of enumeration elements list.
EXTSEL2 : External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
adc_ext_trg0
0x1 : B_0x1
adc_ext_trg1
0x2 : B_0x2
adc_ext_trg2
0x3 : B_0x3
adc_ext_trg3
0x4 : B_0x4
adc_ext_trg4
0x5 : B_0x5
adc_ext_trg5
0x6 : B_0x6
adc_ext_trg6
0x7 : B_0x7
adc_ext_trg7
0x1F : B_0x1F
adc_ext_trg31
End of enumeration elements list.
EXTSEL3 : External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
adc_ext_trg0
0x1 : B_0x1
adc_ext_trg1
0x2 : B_0x2
adc_ext_trg2
0x3 : B_0x3
adc_ext_trg3
0x4 : B_0x4
adc_ext_trg4
0x5 : B_0x5
adc_ext_trg5
0x6 : B_0x6
adc_ext_trg6
0x7 : B_0x7
adc_ext_trg7
0x1F : B_0x1F
adc_ext_trg31
End of enumeration elements list.
EXTSEL4 : External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
adc_ext_trg0
0x1 : B_0x1
adc_ext_trg1
0x2 : B_0x2
adc_ext_trg2
0x3 : B_0x3
adc_ext_trg3
0x4 : B_0x4
adc_ext_trg4
0x5 : B_0x5
adc_ext_trg5
0x6 : B_0x6
adc_ext_trg6
0x7 : B_0x7
adc_ext_trg7
0x1F : B_0x1F
adc_ext_trg31
End of enumeration elements list.
EXTEN : External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Hardware trigger detection disabled (conversions can be launched by software)
0x1 : B_0x1
Hardware trigger detection on the rising edge
0x2 : B_0x2
Hardware trigger detection on the falling edge
0x3 : B_0x3
Hardware trigger detection on both the rising and falling edges
End of enumeration elements list.
OVRMOD : Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC_DR register is preserved with the old data when an overrun is detected.
0x1 : B_0x1
ADC_DR register is overwritten with the last conversion result when an overrun is detected.
End of enumeration elements list.
CONT : Single / Continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Single conversion mode
0x1 : B_0x1
Continuous conversion mode
End of enumeration elements list.
AUTDLY : Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Auto-delayed conversion mode off
0x1 : B_0x1
Auto-delayed conversion mode on
End of enumeration elements list.
ALIGN : Data alignment This bit is set and cleared by software to select right or left alignment. Refer to register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right alignment
0x1 : B_0x1
Left alignment
End of enumeration elements list.
DISCEN : Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Discontinuous mode for regular channels disabled
0x1 : B_0x1
Discontinuous mode for regular channels enabled
End of enumeration elements list.
DISCNUM : Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 channel
0x1 : B_0x1
2 channels
0x7 : B_0x7
8 channels
End of enumeration elements list.
JDISCEN : Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Discontinuous mode on injected channels disabled
0x1 : B_0x1
Discontinuous mode on injected channels enabled
End of enumeration elements list.
JQM : JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR.
0x1 : B_0x1
JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence.
End of enumeration elements list.
AWD1SGL : Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 enabled on all channels
0x1 : B_0x1
Analog watchdog 1 enabled on a single channel
End of enumeration elements list.
AWD1EN : Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 disabled on regular channels
0x1 : B_0x1
Analog watchdog 1 enabled on regular channels
End of enumeration elements list.
JAWD1EN : Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 disabled on injected channels
0x1 : B_0x1
Analog watchdog 1 enabled on injected channels
End of enumeration elements list.
JAUTO : Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Automatic injected group conversion disabled
0x1 : B_0x1
Automatic injected group conversion enabled
End of enumeration elements list.
AWD1CH : Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
bits : 26 - 30 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog input channel 0 monitored by AWD1
0x1 : B_0x1
ADC analog input channel 1 monitored by AWD1
0x12 : B_0x12
ADC analog input channel 18 monitored by AWD1
End of enumeration elements list.
JQDIS : Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected Queue enabled
0x1 : B_0x1
Injected Queue disabled
End of enumeration elements list.
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