Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
ADC common status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDY_MST : Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
bits : 0 - 0 (1 bit)
access : read-only
EOSMP_MST : End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
bits : 1 - 1 (1 bit)
access : read-only
EOC_MST : End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
bits : 2 - 2 (1 bit)
access : read-only
EOS_MST : End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
bits : 3 - 3 (1 bit)
access : read-only
OVR_MST : Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
bits : 4 - 4 (1 bit)
access : read-only
JEOC_MST : End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
bits : 5 - 5 (1 bit)
access : read-only
JEOS_MST : End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
bits : 6 - 6 (1 bit)
access : read-only
AWD1_MST : Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
bits : 7 - 7 (1 bit)
access : read-only
AWD2_MST : Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
bits : 8 - 8 (1 bit)
access : read-only
AWD3_MST : Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
bits : 9 - 9 (1 bit)
access : read-only
JQOVF_MST : Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
bits : 10 - 10 (1 bit)
access : read-only
ADC common control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMODE : ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
adc_ker_ck (x = 3) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC))
0x1 : B_0x1
adc_hclk/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0XXX in RCC_CFGR register) and if the system clock has a 50% duty cycle.
0x2 : B_0x2
adc_hclk/2 (Synchronous clock mode)
0x3 : B_0x3
adc_hclk/4 (Synchronous clock mode)
End of enumeration elements list.
PRESC : ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.
bits : 18 - 21 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
input ADC clock not divided
0x1 : B_0x1
input ADC clock divided by 2
0x2 : B_0x2
input ADC clock divided by 4
0x3 : B_0x3
input ADC clock divided by 6
0x4 : B_0x4
input ADC clock divided by 8
0x5 : B_0x5
input ADC clock divided by 10
0x6 : B_0x6
input ADC clock divided by 12
0x7 : B_0x7
input ADC clock divided by 16
0x8 : B_0x8
input ADC clock divided by 32
0x9 : B_0x9
input ADC clock divided by 64
0xA : B_0xA
input ADC clock divided by 128
0xB : B_0xB
input ADC clock divided by 256
End of enumeration elements list.
VREFEN : VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VREFINT channel disabled
0x1 : B_0x1
VREFINT channel enabled
End of enumeration elements list.
TSEN : VSENSE enable This bit is set and cleared by software to control VSENSE.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Temperature sensor channel disabled
0x1 : B_0x1
Temperature sensor channel enabled
End of enumeration elements list.
VBATEN : VBAT enable This bit is set and cleared by software to control.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VBAT channel disabled
0x1 : B_0x1
VBAT channel enabled
End of enumeration elements list.
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