\n

CORDIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

CORDIC_CSR (CSR)

CORDIC_WDATA (WDATA)

CORDIC_RDATA (RDATA)


CORDIC_CSR (CSR)

CORDIC control/status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORDIC_CSR CORDIC_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNC PRECISION SCALE IEN DMAREN DMAWEN NRES NARGS RESSIZE ARGSIZE RRDY

FUNC : Function
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Cosine

0x1 : B_0x1

Sine

End of enumeration elements list.

PRECISION : Precision required (number of iterations) To determine the number of iterations needed for a given accuracy refer to . Note that for most functions, the recommended range for this field is 3 to 6.
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x1 : B_0x1

(Number of iterations)/4

0x2 : B_0x2

(Number of iterations)/4

0x3 : B_0x3

(Number of iterations)/4

0x4 : B_0x4

(Number of iterations)/4

0x5 : B_0x5

(Number of iterations)/4

0x6 : B_0x6

(Number of iterations)/4

0x7 : B_0x7

(Number of iterations)/4

0x8 : B_0x8

(Number of iterations)/4

0x9 : B_0x9

(Number of iterations)/4

0xa : B_0xa

(Number of iterations)/4

0xb : B_0xb

(Number of iterations)/4

0xc : B_0xc

(Number of iterations)/4

0xd : B_0xd

(Number of iterations)/4

0xe : B_0xe

(Number of iterations)/4

0xf : B_0xf

(Number of iterations)/4

End of enumeration elements list.

SCALE : Scaling factor The value of this field indicates the scaling factor applied to the arguments and/or results. A value n implies that the arguments have been multiplied by a factor 2-n, and/or the results need to be multiplied by 2n. Refer to for the applicability of the scaling factor for each function and the appropriate range.
bits : 8 - 10 (3 bit)
access : read-write

IEN : Enable interrupt. This bit is set and cleared by software. A read returns the current state of the bit.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Disabled. No interrupt requests are generated.

0x1 : B_0x1

Enabled. An interrupt request is generated whenever the RRDY flag is set.

End of enumeration elements list.

DMAREN : Enable DMA read channel This bit is set and cleared by software. A read returns the current state of the bit.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Disabled. No DMA read requests are generated.

0x1 : B_0x1

Enabled. Requests are generated on the DMA read channel whenever the RRDY flag is set.

End of enumeration elements list.

DMAWEN : Enable DMA write channel This bit is set and cleared by software. A read returns the current state of the bit.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Disabled. No DMA write requests are generated.

0x1 : B_0x1

Enabled. Requests are generated on the DMA write channel whenever no operation is pending

End of enumeration elements list.

NRES : Number of results in the CORDIC_RDATA register Reads return the current state of the bit.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Only one 32-bit value (or two 16-bit values if RESSIZE = 1) is transferred to the CORDIC_RDATA register on completion of the next calculation. One read from CORDIC_RDATA resets the RRDY flag.

0x1 : B_0x1

Two 32-bit values are transferred to the CORDIC_RDATA register on completion of the next calculation. Two reads from CORDIC_RDATA are necessary to reset the RRDY flag.

End of enumeration elements list.

NARGS : Number of arguments expected by the CORDIC_WDATA register Reads return the current state of the bit.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Only one 32-bit write (or two 16-bit values if ARGSIZE = 1) is needed for the next calculation.

0x1 : B_0x1

Two 32-bit values must be written to the CORDIC_WDATA register to trigger the next calculation.

End of enumeration elements list.

RESSIZE : Width of output data RESSIZE selects the number of bits used to represent output data. If 32-bit data is selected, the CORDIC_RDATA register contains results in q1.31 format. If 16-bit data is selected, the least significant half-word of CORDIC_RDATA contains the primary result (RES1) in q1.15 format, and the most significant half-word contains the secondary result (RES2), also in q1.15 format.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

32-bit

0x1 : B_0x1

16-bit

End of enumeration elements list.

ARGSIZE : Width of input data ARGSIZE selects the number of bits used to represent input data. If 32-bit data is selected, the CORDIC_WDATA register expects arguments in q1.31 format. If 16-bit data is selected, the CORDIC_WDATA register expects arguments in q1.15 format. The primary argument (ARG1) is written to the least significant half-word, and the secondary argument (ARG2) to the most significant half-word.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

32-bit

0x1 : B_0x1

16-bit

End of enumeration elements list.

RRDY : Result ready flag This bit is set by hardware when a CORDIC operation completes. It is reset by hardware when the CORDIC_RDATA register is read (NRES+1) times. When this bit is set, if the IEN bit is also set, the CORDIC interrupt is asserted. If the DMAREN bit is set, a DMA read channel request is generated. While this bit is set, no new calculation is started.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

No new result in output register

0x1 : B_0x1

CORDIC_RDATA register contains new data.

End of enumeration elements list.


CORDIC_WDATA (WDATA)

CORDIC argument register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORDIC_WDATA CORDIC_WDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARG

ARG : Function input arguments This register is programmed with the input arguments for the function selected in the CORDIC_CSR register FUNC field. If 32-bit format is selected (CORDIC_CSR.ARGSIZE = 0) and two input arguments are required (CORDIC_CSR.NARGS = 1), two successive writes are required to this register. The first writes the primary argument (ARG1), the second writes the secondary argument (ARG2). If 32-bit format is selected and only one input argument is required (NARGS = 0), only one write is required to this register, containing the primary argument (ARG1). If 16-bit format is selected (CORDIC_CSR.ARGSIZE = 1), one write to this register contains both arguments. The primary argument (ARG1) is in the lower half, ARG[15:0], and the secondary argument (ARG2) is in the upper half, ARG[31:16]. In this case, NARGS must be set to 0. Refer to for the arguments required by each function, and their permitted range. When the required number of arguments has been written, the CORDIC evaluates the function designated by CORDIC_CSR.FUNC using the supplied input arguments, provided any previous calculation has completed. If a calculation is ongoing, the ARG1 and ARG 2 values are held pending until the calculation is completed and the results read. During this time, a write to the register cancels the pending operation and overwrite the argument data.
bits : 0 - 31 (32 bit)
access : write-only


CORDIC_RDATA (RDATA)

CORDIC result register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORDIC_RDATA CORDIC_RDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES

RES : Function result If 32-bit format is selected (CORDIC_CSR.RESSIZE = 0) and two output values are expected (CORDIC_CSR.NRES = 1), this register must be read twice when the RRDY flag is set. The first read fetches the primary result (RES1). The second read fetches the secondary result (RES2) and resets RRDY. If 32-bit format is selected and only one output value is expected (NRES = 0), only one read of this register is required to fetch the primary result (RES1) and reset the RRDY flag. If 16-bit format is selected (CORDIC_CSR.RESSIZE = 1), this register contains the primary result (RES1) in the lower half, RES[15:0], and the secondary result (RES2) in the upper half, RES[31:16]. In this case, NRES must be set to 0, and only one read performed. A read from this register resets the RRDY flag in the CORDIC_CSR register.
bits : 0 - 31 (32 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.