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DBGMCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

IDC

APB3FZ1

APB3FZ2

APB1LFZ1

CR

APB1LFZ2

APB2FZ1

APB2FZ2

APB4FZ1

APB4FZ2


IDC

DBGMCU Identity Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDC IDC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device ID
bits : 0 - 11 (12 bit)

REV_ID : Revision
bits : 16 - 31 (16 bit)


APB3FZ1

DBGMCU APB3 peripheral freeze register CPU1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3FZ1 APB3FZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDG1

WWDG1 : WWDG1 stop in debug
bits : 6 - 6 (1 bit)


APB3FZ2

DBGMCU APB3 peripheral freeze register CPU2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3FZ2 APB3FZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDG1

WWDG1 : WWDG1 stop in debug
bits : 6 - 6 (1 bit)


APB1LFZ1

DBGMCU APB1L peripheral freeze register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LFZ1 APB1LFZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM2 DBG_TIM3 DBG_TIM4 DBG_TIM5 DBG_TIM6 DBG_TIM7 DBG_TIM12 DBG_TIM13 DBG_TIM14 DBG_LPTIM1 DBG_WWDG2 DBG_I2C1 DBG_I2C2 DBG_I2C3

DBG_TIM2 : TIM2 stop in debug
bits : 0 - 0 (1 bit)

DBG_TIM3 : TIM3 stop in debug
bits : 1 - 1 (1 bit)

DBG_TIM4 : TIM4 stop in debug
bits : 2 - 2 (1 bit)

DBG_TIM5 : TIM5 stop in debug
bits : 3 - 3 (1 bit)

DBG_TIM6 : TIM6 stop in debug
bits : 4 - 4 (1 bit)

DBG_TIM7 : TIM7 stop in debug
bits : 5 - 5 (1 bit)

DBG_TIM12 : TIM12 stop in debug
bits : 6 - 6 (1 bit)

DBG_TIM13 : TIM13 stop in debug
bits : 7 - 7 (1 bit)

DBG_TIM14 : TIM14 stop in debug
bits : 8 - 8 (1 bit)

DBG_LPTIM1 : LPTIM1 stop in debug
bits : 9 - 9 (1 bit)

DBG_WWDG2 : WWDG2 stop in debug
bits : 11 - 11 (1 bit)

DBG_I2C1 : I2C1 SMBUS timeout stop in debug
bits : 21 - 21 (1 bit)

DBG_I2C2 : I2C2 SMBUS timeout stop in debug
bits : 22 - 22 (1 bit)

DBG_I2C3 : I2C3 SMBUS timeout stop in debug
bits : 23 - 23 (1 bit)


CR

DBGMCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGSLPD1 DBGSTPD1 DBGSTBD1 DBGSLPD2 DBGSTPD2 DBGSTBD2 DBGSTPD3 DBGSTBD3 TRACECLKEN D1DBGCKEN D3DBGCKEN TRGOEN

DBGSLPD1 : Allow D1 domain debug in Sleep mode
bits : 0 - 0 (1 bit)

DBGSTPD1 : Allow D1 domain debug in Stop mode
bits : 1 - 1 (1 bit)

DBGSTBD1 : Allow D1 domain debug in Standby mode
bits : 2 - 2 (1 bit)

DBGSLPD2 : Allow D2 domain debug in Sleep mode
bits : 3 - 3 (1 bit)

DBGSTPD2 : Allow D2 domain debug in Stop mode
bits : 4 - 4 (1 bit)

DBGSTBD2 : Allow D2 domain debug in Standby mode
bits : 5 - 5 (1 bit)

DBGSTPD3 : Allow debug in D3 Stop mode
bits : 7 - 7 (1 bit)

DBGSTBD3 : Allow debug in D3 Standby mode
bits : 8 - 8 (1 bit)

TRACECLKEN : Trace port clock enable
bits : 20 - 20 (1 bit)

D1DBGCKEN : D1 debug clock enable
bits : 21 - 21 (1 bit)

D3DBGCKEN : D3 debug clock enable
bits : 22 - 22 (1 bit)

TRGOEN : External trigger output enable
bits : 28 - 28 (1 bit)


APB1LFZ2

DBGMCU APB1L peripheral freeze register CPU2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LFZ2 APB1LFZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM2 DBG_TIM3 DBG_TIM4 DBG_TIM5 DBG_TIM6 DBG_TIM7 DBG_TIM12 DBG_TIM13 DBG_TIM14 DBG_LPTIM1 DBG_WWDG2 DBG_I2C1 DBG_I2C2 DBG_I2C3

DBG_TIM2 : TIM2 stop in debug
bits : 0 - 0 (1 bit)

DBG_TIM3 : TIM3 stop in debug
bits : 1 - 1 (1 bit)

DBG_TIM4 : TIM4 stop in debug
bits : 2 - 2 (1 bit)

DBG_TIM5 : TIM5 stop in debug
bits : 3 - 3 (1 bit)

DBG_TIM6 : TIM6 stop in debug
bits : 4 - 4 (1 bit)

DBG_TIM7 : TIM4 stop in debug
bits : 5 - 5 (1 bit)

DBG_TIM12 : TIM12 stop in debug
bits : 6 - 6 (1 bit)

DBG_TIM13 : TIM13 stop in debug
bits : 7 - 7 (1 bit)

DBG_TIM14 : TIM14 stop in debug
bits : 8 - 8 (1 bit)

DBG_LPTIM1 : LPTIM1 stop in debug
bits : 9 - 9 (1 bit)

DBG_WWDG2 : WWDG2 stop in debug
bits : 11 - 11 (1 bit)

DBG_I2C1 : I2C1 SMBUS timeout stop in debug
bits : 21 - 21 (1 bit)

DBG_I2C2 : I2C2 SMBUS timeout stop in debug
bits : 22 - 22 (1 bit)

DBG_I2C3 : I2C3 SMBUS timeout stop in debug
bits : 23 - 23 (1 bit)


APB2FZ1

DBGMCU APB2 peripheral freeze register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2FZ1 APB2FZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM1 DBG_TIM8 DBG_TIM15 DBG_TIM16 DBG_TIM17

DBG_TIM1 : TIM1 stop in debug
bits : 0 - 0 (1 bit)

DBG_TIM8 : TIM8 stop in debug
bits : 1 - 1 (1 bit)

DBG_TIM15 : TIM15 stop in debug
bits : 16 - 16 (1 bit)

DBG_TIM16 : TIM16 stop in debug
bits : 17 - 17 (1 bit)

DBG_TIM17 : TIM17 stop in debug
bits : 18 - 18 (1 bit)


APB2FZ2

DBGMCU APB2 peripheral freeze register CPU2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2FZ2 APB2FZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM1 DBG_TIM8 DBG_TIM15 DBG_TIM16 DBG_TIM17

DBG_TIM1 : TIM1 stop in debug
bits : 0 - 0 (1 bit)

DBG_TIM8 : TIM8 stop in debug
bits : 1 - 1 (1 bit)

DBG_TIM15 : TIM15 stop in debug
bits : 16 - 16 (1 bit)

DBG_TIM16 : TIM16 stop in debug
bits : 17 - 17 (1 bit)

DBG_TIM17 : TIM17 stop in debug
bits : 18 - 18 (1 bit)


APB4FZ1

DBGMCU APB4 peripheral freeze register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB4FZ1 APB4FZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_I2C4 DBG_LPTIM2 DBG_LPTIM3 DBG_LPTIM4 DBG_LPTIM5 DBG_RTC DBG_WDGLSD1 DBG_WDGLSD2

DBG_I2C4 : I2C4 SMBUS timeout stop in debug
bits : 7 - 7 (1 bit)

DBG_LPTIM2 : LPTIM2 stop in debug
bits : 9 - 9 (1 bit)

DBG_LPTIM3 : LPTIM2 stop in debug
bits : 10 - 10 (1 bit)

DBG_LPTIM4 : LPTIM4 stop in debug
bits : 11 - 11 (1 bit)

DBG_LPTIM5 : LPTIM5 stop in debug
bits : 12 - 12 (1 bit)

DBG_RTC : RTC stop in debug
bits : 16 - 16 (1 bit)

DBG_WDGLSD1 : Independent watchdog for D1 stop in debug
bits : 18 - 18 (1 bit)

DBG_WDGLSD2 : Independent watchdog for D2 stop in debug
bits : 19 - 19 (1 bit)


APB4FZ2

DBGMCU APB4 peripheral freeze register CPU2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB4FZ2 APB4FZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_I2C4 DBG_LPTIM2 DBG_LPTIM3 DBG_LPTIM4 DBG_LPTIM5 DBG_RTC DBG_WDGLSD1 DBG_WDGLSD2

DBG_I2C4 : I2C4 SMBUS timeout stop in debug
bits : 7 - 7 (1 bit)

DBG_LPTIM2 : LPTIM2 stop in debug
bits : 9 - 9 (1 bit)

DBG_LPTIM3 : LPTIM2 stop in debug
bits : 10 - 10 (1 bit)

DBG_LPTIM4 : LPTIM4 stop in debug
bits : 11 - 11 (1 bit)

DBG_LPTIM5 : LPTIM5 stop in debug
bits : 12 - 12 (1 bit)

DBG_RTC : RTC stop in debug
bits : 16 - 16 (1 bit)

DBG_WDGLSD1 : LS watchdog for D1 stop in debug
bits : 18 - 18 (1 bit)

DBG_WDGLSD2 : LS watchdog for D2 stop in debug
bits : 19 - 19 (1 bit)



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