Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
PSSI control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKPOL : Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Falling edge active for inputs or rising edge active for outputs
0x1 : B_0x1
Rising edge active for inputs or falling edge active for outputs.
End of enumeration elements list.
DEPOL : Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PSSI_DE active low (0 indicates that data is valid)
0x1 : B_0x1
PSSI_DE active high (1 indicates that data is valid)
End of enumeration elements list.
RDYPOL : Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PSSI_RDY active low (0 indicates that the receiver is ready to receive)
0x1 : B_0x1
PSSI_RDY active high (1 indicates that the receiver is ready to receive)
End of enumeration elements list.
EDM : Extended data mode
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interface captures 8-bit data on every parallel data clock
0x1 : B_0x1
Reserved, must not be selected
0x2 : B_0x2
Reserved, must not be selected
0x3 : B_0x3
The interface captures 16-bit data on every parallel data clock
End of enumeration elements list.
ENABLE : PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PSSI disabled
0x1 : B_0x1
PSSI enabled
End of enumeration elements list.
DERDYCFG : Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity.
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PSSI_DE and PSSI_RDY both disabled
0x1 : B_0x1
Only PSSI_RDY enabled
0x2 : B_0x2
Only PSSI_DE enabled
0x3 : B_0x3
Both PSSI_RDY and PSSI_DE alternate functions enabled
0x4 : B_0x4
Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin (see )
0x5 : B_0x5
Only PSSI_RDY function enabled, but mapped to PSSI_DE pin
0x6 : B_0x6
Only PSSI_DE function enabled, but mapped to PSSI_RDY pin
0x7 : B_0x7
Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin (see )
End of enumeration elements list.
DMAEN : DMA enable bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled.
0x1 : B_0x1
DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR.
End of enumeration elements list.
OUTEN : Data direction selection bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Receive mode: data is input synchronously with PSSI_PDCK
0x1 : B_0x1
Transmit mode: data is output synchronously with PSSI_PDCK
End of enumeration elements list.
PSSI masked interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR_MIS : Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No interrupt is generated when an overrun/underrun error occurs
0x1 : B_0x1
An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER.
End of enumeration elements list.
PSSI interrupt clear register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR_ISC : Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS.
bits : 1 - 1 (1 bit)
access : write-only
PSSI data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYTE0 : Data byte 0
bits : 0 - 7 (8 bit)
access : read-write
BYTE1 : Data byte 1
bits : 8 - 15 (8 bit)
access : read-write
BYTE2 : Data byte 2
bits : 16 - 23 (8 bit)
access : read-write
BYTE3 : Data byte 3
bits : 24 - 31 (8 bit)
access : read-write
PSSI status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTT4B : FIFO is ready to transfer four bytes
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x1 : B_0x1
FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO.
0x0 : B_0x0
FIFO is not ready for a four-byte transfer
End of enumeration elements list.
RTT1B : FIFO is ready to transfer one byte
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x1 : B_0x1
FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO.
0x0 : B_0x0
FIFO is not ready for a 1-byte transfer
End of enumeration elements list.
PSSI raw interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR_RIS : Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No overrun/underrun occurred
0x1 : B_0x1
An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode.
End of enumeration elements list.
PSSI interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR_IE : Data buffer overrun/underrun interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No interrupt generation
0x1 : B_0x1
An interrupt is generated if either an overrun or an underrun error occurred.
End of enumeration elements list.
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