Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x30C byte (0x0)
mem_usage : registers
protection :
OTFDEC region 1 configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG_EN : region on-the-fly decryption enable Note: When this bit is set region context (version, key, nonce) must be valid or garbage will be decrypted.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
On-the-fly decryption is disabled for this region.
0x1 : B_0x1
On-the-fly decryption is enabled for this region. Data are XORed with the corresponding keystream.
End of enumeration elements list.
CONFIGLOCK : region config lock This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. Setting this bit forces KEYLOCK bit to “1”.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are allowed.
0x1 : B_0x1
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are ignored until next OTFDEC reset.
End of enumeration elements list.
KEYLOCK : region key lock This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region KEYRx registers are allowed.
0x1 : B_0x1
Writes to this region KEYRx registers are ignored until next OTFDEC reset. KEYCRC bitfield is locked.
End of enumeration elements list.
MODE : operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. When either of the MODE bits are changed the region’s key and associated CRC are zeroed.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Only instruction accesses are decrypted.
0x1 : B_0x1
Only data accesses are decrypted.
0x2 : B_0x2
All read accesses are decrypted (instruction or data).
0x3 : B_0x3
Only instruction accesses are decrypted, and enhanced encryption mode is activated.
End of enumeration elements list.
KEYCRC : region key 8-bit CRC When KEYLOCK=0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK=1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in this manual. This field is read only. Note: CRC information is updated only after the last bit of the key has been written.
bits : 8 - 15 (8 bit)
access : read-only
REGx_VERSION : region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in the RxCFGR register.
bits : 16 - 31 (16 bit)
access : read-write
OTFDEC region 1 start address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_START_ADDR : Region AXI start address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits and the 12 LSB bits return zero.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 1 end address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_END_ADDR : Region AXI end address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set, and RxENDADDR must be strictly greater than RxSTARTADDR to be valid. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits returns zeros and the 12 LSB bits return ones.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 1 nonce register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 1 nonce register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [63:32] Refer to the OTFDEC_RxNONCER0 register for description of the NONCE[63:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC interrupt status register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEIF : Security Error Interrupt Flag status This bit is set by hardware and read only by application. Bit is set when at least one security error has been detected (illegal access to keys, illegal write on locked configuration). Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1”.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No security error status. No interrupt pending.
0x1 : B_0x1
Security error flag status, with interrupt pending. Actual interrupt generation is dependent on OTFDEC_IER corresponding bit SEIE.
End of enumeration elements list.
XONEIF : Execute-only execute-Never Error Interrupt Flag status This bit is set by hardware and read only by application. Bit is set when a read access and not an instruction fetch is detected on any encrypted region with MODE bits set to 00 or 11. It is also set when an instruction fetch and not a read access is detected on any encrypted region with MODE bits set to 01. Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1”.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No execute-only error status. No interrupt pending.
0x1 : B_0x1
Read access detected on one region with MODE bits set to 00 or 11, or execute access detected on one region with MODE bits set to 01. OTFDEC returns a zeroed value for the illegal access, and an optional interrupt is generated if bit XONEIE is set to “1” in OTFDEC_IER register.
End of enumeration elements list.
KEIF : Key Error Interrupt Flag status This bit is set by hardware and read only by application. Bit is set when a read access occurs on any encrypted region following the reset of the key registers by an abort event (tamper detection, unauthorized debugger connection, untrusted boot, RDP level regression). Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1”. After KEIF is set any subsequent read to any enabled encrypted region returns a zeroed value. This state remains until OTFDEC keys are initialized again.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
OTFDEC is operating properly.
0x1 : B_0x1
Read access detected on an enabled encrypted region following an abort event. OTFDEC returns a zeroed value for the read, and an optional interrupt is generated if bit KEIE is set to “1” in OTFDEC_IER register.
End of enumeration elements list.
OTFDEC interrupt clear register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEIF : Security Error Interrupt Flag clear This bit is written by application, and always reads as 0.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
SEIF flag status is not affected
0x1 : B_0x1
SEIF flag status is cleared in OTFDEC_ISR register
End of enumeration elements list.
XONEIF : Execute-only execute-Never Error Interrupt Flag clear This bit is written by application, and always reads as 0.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
XONEIF flag status is not affected
0x1 : B_0x1
XONEIF flag status is cleared in OTFDEC_ISR register
End of enumeration elements list.
KEIF : Key Error Interrupt Flag clear This bit is written by application, and always reads as 0. Note: Clearing KEIF does not solve the source of the problem (bad key registers). To be able to read or execute again any encrypted region, OTFDEC key registers must properly initialized, again.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
KEIF flag status is not affected
0x1 : B_0x1
KEIF flag status is cleared in OTFDEC_ISR register
End of enumeration elements list.
OTFDEC interrupt enable register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEIE : Security Error Interrupt Enable This bit is read and written by application. It controls the OTFDEC interrupt generation when SEIF flag status is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt generation on security error SEIF is disabled (masked)
0x1 : B_0x1
Interrupt generation on security error SEIF is enabled (not masked)
End of enumeration elements list.
XONEIE : Execute-only execute-Never Error Interrupt Enable This bit is read and written by application. It controls the OTFDEC interrupt generation when XONEIF flag status is set.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt generation on execute-only error XONEIF is disabled (masked)
0x1 : B_0x1
Interrupt generation on execute-only error XONEIF is enabled (not masked)
End of enumeration elements list.
KEIE : Key Error Interrupt Enable This bit is read and written by application. It controls the OTFDEC interrupt generation when KEIF flag status is set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt generation on key error flag KEIF is disabled (masked)
0x1 : B_0x1
Interrupt generation on key error flag KEIF is enabled (not masked)
End of enumeration elements list.
OTFDEC region 1 key register 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Reading this register returns a zero value. Writing this register while the region CONFIGLOCK or KEYLOCK bit is set in the RxCFGR register will be discarded. Note: When application successfully changes MODE bits in RxCFGR register RxKEYR registers and associated KEYCRC are erased.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 1 key register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [63:32] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 1 key register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [95:64] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 1 key register 3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [127:96] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 2 configuration register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG_EN : region on-the-fly decryption enable Note: When this bit is set region context (version, key, nonce) must be valid or garbage will be decrypted.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
On-the-fly decryption is disabled for this region.
0x1 : B_0x1
On-the-fly decryption is enabled for this region. Data are XORed with the corresponding keystream.
End of enumeration elements list.
CONFIGLOCK : region config lock This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. Setting this bit forces KEYLOCK bit to “1”.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are allowed.
0x1 : B_0x1
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are ignored until next OTFDEC reset.
End of enumeration elements list.
KEYLOCK : region key lock This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region KEYRx registers are allowed.
0x1 : B_0x1
Writes to this region KEYRx registers are ignored until next OTFDEC reset. KEYCRC bitfield is locked.
End of enumeration elements list.
MODE : operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. When either of the MODE bits are changed the region’s key and associated CRC are zeroed.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Only instruction accesses are decrypted.
0x1 : B_0x1
Only data accesses are decrypted.
0x2 : B_0x2
All read accesses are decrypted (instruction or data).
0x3 : B_0x3
Only instruction accesses are decrypted, and enhanced encryption mode is activated.
End of enumeration elements list.
KEYCRC : region key 8-bit CRC When KEYLOCK=0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK=1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in this manual. This field is read only. Note: CRC information is updated only after the last bit of the key has been written.
bits : 8 - 15 (8 bit)
access : read-only
REGx_VERSION : region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in the RxCFGR register.
bits : 16 - 31 (16 bit)
access : read-write
OTFDEC region 2 start address register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_START_ADDR : Region AXI start address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits and the 12 LSB bits return zero.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 2 end address register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_END_ADDR : Region AXI end address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set, and RxENDADDR must be strictly greater than RxSTARTADDR to be valid. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits returns zeros and the 12 LSB bits return ones.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 2 nonce register 0
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 2 nonce register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [63:32] Refer to the OTFDEC_RxNONCER0 register for description of the NONCE[63:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 2 key register 0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Reading this register returns a zero value. Writing this register while the region CONFIGLOCK or KEYLOCK bit is set in the RxCFGR register will be discarded. Note: When application successfully changes MODE bits in RxCFGR register RxKEYR registers and associated KEYCRC are erased.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 2 key register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [63:32] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 2 key register 2
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [95:64] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 2 key register 3
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [127:96] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 3 configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG_EN : region on-the-fly decryption enable Note: When this bit is set region context (version, key, nonce) must be valid or garbage will be decrypted.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
On-the-fly decryption is disabled for this region.
0x1 : B_0x1
On-the-fly decryption is enabled for this region. Data are XORed with the corresponding keystream.
End of enumeration elements list.
CONFIGLOCK : region config lock This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. Setting this bit forces KEYLOCK bit to “1”.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are allowed.
0x1 : B_0x1
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are ignored until next OTFDEC reset.
End of enumeration elements list.
KEYLOCK : region key lock This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region KEYRx registers are allowed.
0x1 : B_0x1
Writes to this region KEYRx registers are ignored until next OTFDEC reset. KEYCRC bitfield is locked.
End of enumeration elements list.
MODE : operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. When either of the MODE bits are changed the region’s key and associated CRC are zeroed.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Only instruction accesses are decrypted.
0x1 : B_0x1
Only data accesses are decrypted.
0x2 : B_0x2
All read accesses are decrypted (instruction or data).
0x3 : B_0x3
Only instruction accesses are decrypted, and enhanced encryption mode is activated.
End of enumeration elements list.
KEYCRC : region key 8-bit CRC When KEYLOCK=0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK=1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in this manual. This field is read only. Note: CRC information is updated only after the last bit of the key has been written.
bits : 8 - 15 (8 bit)
access : read-only
REGx_VERSION : region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in the RxCFGR register.
bits : 16 - 31 (16 bit)
access : read-write
OTFDEC region 3 start address register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_START_ADDR : Region AXI start address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits and the 12 LSB bits return zero.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 3 end address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_END_ADDR : Region AXI end address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set, and RxENDADDR must be strictly greater than RxSTARTADDR to be valid. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits returns zeros and the 12 LSB bits return ones.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 3 nonce register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 3 nonce register 1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [63:32] Refer to the OTFDEC_RxNONCER0 register for description of the NONCE[63:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 3 key register 0
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Reading this register returns a zero value. Writing this register while the region CONFIGLOCK or KEYLOCK bit is set in the RxCFGR register will be discarded. Note: When application successfully changes MODE bits in RxCFGR register RxKEYR registers and associated KEYCRC are erased.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 3 key register 1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [63:32] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 3 key register 2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [95:64] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 3 key register 3
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [127:96] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 4 configuration register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG_EN : region on-the-fly decryption enable Note: When this bit is set region context (version, key, nonce) must be valid or garbage will be decrypted.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
On-the-fly decryption is disabled for this region.
0x1 : B_0x1
On-the-fly decryption is enabled for this region. Data are XORed with the corresponding keystream.
End of enumeration elements list.
CONFIGLOCK : region config lock This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. Setting this bit forces KEYLOCK bit to “1”.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are allowed.
0x1 : B_0x1
Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are ignored until next OTFDEC reset.
End of enumeration elements list.
KEYLOCK : region key lock This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writes to this region KEYRx registers are allowed.
0x1 : B_0x1
Writes to this region KEYRx registers are ignored until next OTFDEC reset. KEYCRC bitfield is locked.
End of enumeration elements list.
MODE : operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. When either of the MODE bits are changed the region’s key and associated CRC are zeroed.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Only instruction accesses are decrypted.
0x1 : B_0x1
Only data accesses are decrypted.
0x2 : B_0x2
All read accesses are decrypted (instruction or data).
0x3 : B_0x3
Only instruction accesses are decrypted, and enhanced encryption mode is activated.
End of enumeration elements list.
KEYCRC : region key 8-bit CRC When KEYLOCK=0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK=1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in this manual. This field is read only. Note: CRC information is updated only after the last bit of the key has been written.
bits : 8 - 15 (8 bit)
access : read-only
REGx_VERSION : region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in the RxCFGR register.
bits : 16 - 31 (16 bit)
access : read-write
OTFDEC region 4 start address register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_START_ADDR : Region AXI start address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits and the 12 LSB bits return zero.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 4 end address register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_END_ADDR : Region AXI end address This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set, and RxENDADDR must be strictly greater than RxSTARTADDR to be valid. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded. Note: When determining the region the first 12 bits (LSB) and the last 4 bits (MSB) are ignored. When this register is accessed in read the 4 MSB bits returns zeros and the 12 LSB bits return ones.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 4 nonce register 0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Writing this register while the region CONFIGLOCK bit in the RxCFGR register is set will be discarded.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 4 nonce register 1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_NONCE : Region nonce, bits [63:32] Refer to the OTFDEC_RxNONCER0 register for description of the NONCE[63:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write
OTFDEC region 4 key register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [31:0] This register must be written before the region corresponding REG_EN bit in the RxCFGR register is set. Reading this register returns a zero value. Writing this register while the region CONFIGLOCK or KEYLOCK bit is set in the RxCFGR register will be discarded. Note: When application successfully changes MODE bits in RxCFGR register RxKEYR registers and associated KEYCRC are erased.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 4 key register 1
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [63:32] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 4 key register 2
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [95:64] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
OTFDEC region 4 key register 3
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGx_KEY : Region key, bits [127:96] Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield.
bits : 0 - 31 (32 bit)
access : write-only
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