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Ethernet

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

MTLOMR

MTLTxQOMR

MTLTxQUR

MTLTxQDR

MTLQICSR

MTLRxQOMR

MTLRxQMPOCR

MTLRxQDR

MTLISR


MTLOMR

Operating mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLOMR MTLOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTXSTS CNTPRST CNTCLR

DTXSTS : DTXSTS
bits : 1 - 1 (1 bit)

CNTPRST : CNTPRST
bits : 8 - 8 (1 bit)

CNTCLR : CNTCLR
bits : 9 - 9 (1 bit)


MTLTxQOMR

Tx queue operating mode Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLTxQOMR MTLTxQOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTQ TSF TXQEN TTC TQS

FTQ : Flush Transmit Queue
bits : 0 - 0 (1 bit)
access : read-write

TSF : Transmit Store and Forward
bits : 1 - 1 (1 bit)
access : read-write

TXQEN : Transmit Queue Enable
bits : 2 - 3 (2 bit)
access : read-only

TTC : Transmit Threshold Control
bits : 4 - 6 (3 bit)
access : read-write

TQS : Transmit Queue Size
bits : 16 - 18 (3 bit)
access : read-write


MTLTxQUR

Tx queue underflow register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLTxQUR MTLTxQUR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UFFRMCNT UFCNTOVF

UFFRMCNT : Underflow Packet Counter
bits : 0 - 10 (11 bit)

UFCNTOVF : UFCNTOVF
bits : 11 - 11 (1 bit)


MTLTxQDR

Tx queue debug Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLTxQDR MTLTxQDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXQPAUSED TRCSTS TWCSTS TXQSTS TXSTSFSTS PTXQ STXSTSF

TXQPAUSED : TXQPAUSED
bits : 0 - 0 (1 bit)

TRCSTS : TRCSTS
bits : 1 - 2 (2 bit)

TWCSTS : TWCSTS
bits : 3 - 3 (1 bit)

TXQSTS : TXQSTS
bits : 4 - 4 (1 bit)

TXSTSFSTS : TXSTSFSTS
bits : 5 - 5 (1 bit)

PTXQ : PTXQ
bits : 16 - 18 (3 bit)

STXSTSF : STXSTSF
bits : 20 - 22 (3 bit)


MTLQICSR

Queue interrupt control status Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLQICSR MTLQICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXUNFIS TXUIE RXOVFIS RXOIE

TXUNFIS : TXUNFIS
bits : 0 - 0 (1 bit)

TXUIE : TXUIE
bits : 8 - 8 (1 bit)

RXOVFIS : RXOVFIS
bits : 16 - 16 (1 bit)

RXOIE : RXOIE
bits : 24 - 24 (1 bit)


MTLRxQOMR

Rx queue operating mode register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTLRxQOMR MTLRxQOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC FUP FEP RSF DIS_TCP_EF EHFC RFA RFD RQS

RTC : RTC
bits : 0 - 1 (2 bit)
access : read-write

FUP : FUP
bits : 3 - 3 (1 bit)
access : read-write

FEP : FEP
bits : 4 - 4 (1 bit)
access : read-write

RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write

DIS_TCP_EF : DIS_TCP_EF
bits : 6 - 6 (1 bit)
access : read-write

EHFC : EHFC
bits : 7 - 7 (1 bit)
access : read-write

RFA : RFA
bits : 8 - 10 (3 bit)
access : read-write

RFD : RFD
bits : 14 - 16 (3 bit)
access : read-write

RQS : RQS
bits : 20 - 22 (3 bit)
access : read-only


MTLRxQMPOCR

Rx queue missed packet and overflow counter register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLRxQMPOCR MTLRxQMPOCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVFPKTCNT OVFCNTOVF MISPKTCNT MISCNTOVF

OVFPKTCNT : OVFPKTCNT
bits : 0 - 10 (11 bit)

OVFCNTOVF : OVFCNTOVF
bits : 11 - 11 (1 bit)

MISPKTCNT : MISPKTCNT
bits : 16 - 26 (11 bit)

MISCNTOVF : MISCNTOVF
bits : 27 - 27 (1 bit)


MTLRxQDR

Rx queue debug register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLRxQDR MTLRxQDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWCSTS RRCSTS RXQSTS PRXQ

RWCSTS : RWCSTS
bits : 0 - 0 (1 bit)

RRCSTS : RRCSTS
bits : 1 - 2 (2 bit)

RXQSTS : RXQSTS
bits : 4 - 5 (2 bit)

PRXQ : PRXQ
bits : 16 - 29 (14 bit)


MTLISR

Interrupt status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MTLISR MTLISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q0IS

Q0IS : Queue interrupt status
bits : 0 - 0 (1 bit)



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