CR

SR

DR

RNGEN : Random number generator enable
bits : 2 - 2 (1 bit)

IE : Interrupt enable
bits : 3 - 3 (1 bit)

CED : Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled.
bits : 5 - 5 (1 bit)

DRDY : Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated.
bits : 0 - 0 (1 bit)
access : read-only

CECS : Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1.
bits : 1 - 1 (1 bit)
access : read-only

SECS : Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01)
bits : 2 - 2 (1 bit)
access : read-only

CEIS : Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1.
bits : 5 - 5 (1 bit)
access : read-write

SEIS : Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register.
bits : 6 - 6 (1 bit)
access : read-write

RNDATA : Random data 32-bit random data which are valid when DRDY=1.
bits : 0 - 31 (32 bit)