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DSIHOST

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection :

Registers

DSI_VR

DSI_LCOLCR

DSI_VSCR

DSI_LCVCIDR

DSI_LCCCR

DSI_LPMCCR

DSI_VMCCR

DSI_VPCCR

DSI_LPCR

DSI_VCCCR

DSI_VNPCCR

DSI_VHSACCR

DSI_VHBPCCR

DSI_VLCCR

DSI_VVSACCR

DSI_VVBPCCR

DSI_VVFPCCR

DSI_VVACCR

DSI_LPMCR

DSI_PCR

DSI_GVCIDR

DSI_MCR

DSI_VMCR

DSI_VPCR

DSI_CR

DSI_VCCR

DSI_WCFGR

DSI_WCR

DSI_WIER

DSI_WISR

DSI_WIFCR

DSI_WPCR0

DSI_WPCR1

DSI_WPCR2

DSI_WPCR3

DSI_WPCR4

DSI_WRPCR

DSI_VNPCR

DSI_VHSACR

DSI_VHBPCR

DSI_VLCR

DSI_VVSACR

DSI_VVBPCR

DSI_VVFPCR

DSI_VVACR

DSI_LCCR

DSI_CMCR

DSI_GHCR

DSI_GPDR

DSI_GPSR

DSI_TCCR0

DSI_TCCR1

DSI_CCR

DSI_TCCR2

DSI_TCCR3

DSI_TCCR4

DSI_TCCR5

DSI_CLCR

DSI_CLTCR

DSI_DLTCR

DSI_PCTLR

DSI_PCONFR

DSI_PUCR

DSI_PTTCR

DSI_PSR

DSI_ISR0

DSI_LVCIDR

DSI_ISR1

DSI_IER0

DSI_IER1

DSI_FIR0

DSI_FIR1


DSI_VR

DSI Host version register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VR DSI_VR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION

VERSION : VERSION
bits : 0 - 31 (32 bit)


DSI_LCOLCR

DSI Host LTDC color coding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCOLCR DSI_LCOLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLC LPE

COLC : COLC
bits : 0 - 3 (4 bit)

LPE : LPE
bits : 8 - 8 (1 bit)


DSI_VSCR

DSI Host video shadow control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VSCR DSI_VSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UR

EN : EN
bits : 0 - 0 (1 bit)

UR : UR
bits : 8 - 8 (1 bit)


DSI_LCVCIDR

DSI Host LTDC current VCID register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCVCIDR DSI_LCVCIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : VCID
bits : 0 - 1 (2 bit)


DSI_LCCCR

DSI Host LTDC current color coding register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_LCCCR DSI_LCCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLC LPE

COLC : COLC
bits : 0 - 3 (4 bit)

LPE : LPE
bits : 8 - 8 (1 bit)


DSI_LPMCCR

DSI Host low-power mode current configuration register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_LPMCCR DSI_LPMCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLPSIZE LPSIZE

VLPSIZE : VLPSIZE
bits : 0 - 7 (8 bit)

LPSIZE : LPSIZE
bits : 16 - 23 (8 bit)


DSI_VMCCR

DSI Host video mode current configuration register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VMCCR DSI_VMCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMT LPVSAE LPVBPE LPVFPE LPVAE LPHBPE LPHFE FBTAAE LPCE

VMT : VMT
bits : 0 - 1 (2 bit)

LPVSAE : LPVSAE
bits : 2 - 2 (1 bit)

LPVBPE : LPVBPE
bits : 3 - 3 (1 bit)

LPVFPE : LPVFPE
bits : 4 - 4 (1 bit)

LPVAE : LPVAE
bits : 5 - 5 (1 bit)

LPHBPE : LPHBPE
bits : 6 - 6 (1 bit)

LPHFE : LPHFE
bits : 7 - 7 (1 bit)

FBTAAE : FBTAAE
bits : 8 - 8 (1 bit)

LPCE : LPCE
bits : 9 - 9 (1 bit)


DSI_VPCCR

DSI Host video packet current configuration register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VPCCR DSI_VPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPSIZE

VPSIZE : VPSIZE
bits : 0 - 13 (14 bit)


DSI_LPCR

DSI Host LTDC polarity configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LPCR DSI_LPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEP VSP HSP

DEP : DEP
bits : 0 - 0 (1 bit)

VSP : VSP
bits : 1 - 1 (1 bit)

HSP : HSP
bits : 2 - 2 (1 bit)


DSI_VCCCR

DSI Host video chunks current configuration register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VCCCR DSI_VCCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUMC

NUMC : NUMC
bits : 0 - 12 (13 bit)


DSI_VNPCCR

DSI Host video null packet current configuration register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VNPCCR DSI_VNPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPSIZE

NPSIZE : NPSIZE
bits : 0 - 12 (13 bit)


DSI_VHSACCR

DSI Host video HSA current configuration register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VHSACCR DSI_VHSACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSA

HSA : HSA
bits : 0 - 11 (12 bit)


DSI_VHBPCCR

DSI Host video HBP current configuration register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VHBPCCR DSI_VHBPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBP

HBP : HBP
bits : 0 - 11 (12 bit)


DSI_VLCCR

DSI Host video line current configuration register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VLCCR DSI_VLCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLINE

HLINE : HLINE
bits : 0 - 14 (15 bit)


DSI_VVSACCR

DSI Host video VSA current configuration register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVSACCR DSI_VVSACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSA

VSA : VSA
bits : 0 - 9 (10 bit)


DSI_VVBPCCR

DSI Host video VBP current configuration register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVBPCCR DSI_VVBPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBP

VBP : VBP
bits : 0 - 9 (10 bit)


DSI_VVFPCCR

DSI Host video VFP current configuration register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVFPCCR DSI_VVFPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFP

VFP : VFP
bits : 0 - 9 (10 bit)


DSI_VVACCR

DSI Host video VA current configuration register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVACCR DSI_VVACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VA

VA : VA
bits : 0 - 13 (14 bit)


DSI_LPMCR

DSI Host low-power mode configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LPMCR DSI_LPMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLPSIZE LPSIZE

VLPSIZE : VLPSIZE
bits : 0 - 7 (8 bit)

LPSIZE : LPSIZE
bits : 16 - 23 (8 bit)


DSI_PCR

DSI Host protocol configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCR DSI_PCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETTXE ETRXE BTAE ECCRXE CRCRXE

ETTXE : ETTXE
bits : 0 - 0 (1 bit)

ETRXE : ETRXE
bits : 1 - 1 (1 bit)

BTAE : BTAE
bits : 2 - 2 (1 bit)

ECCRXE : ECCRXE
bits : 3 - 3 (1 bit)

CRCRXE : CRCRXE
bits : 4 - 4 (1 bit)


DSI_GVCIDR

DSI Host generic VCID register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_GVCIDR DSI_GVCIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : VCID
bits : 0 - 1 (2 bit)


DSI_MCR

DSI Host mode configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_MCR DSI_MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDM

CMDM : CMDM
bits : 0 - 0 (1 bit)


DSI_VMCR

DSI Host video mode configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VMCR DSI_VMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMT LPVSAE LPVBPE LPVFPE LPVAE LPHBPE LPHFPE FBTAAE LPCE PGE PGM PGO

VMT : VMT
bits : 0 - 1 (2 bit)

LPVSAE : LPVSAE
bits : 8 - 8 (1 bit)

LPVBPE : LPVBPE
bits : 9 - 9 (1 bit)

LPVFPE : LPVFPE
bits : 10 - 10 (1 bit)

LPVAE : LPVAE
bits : 11 - 11 (1 bit)

LPHBPE : LPHBPE
bits : 12 - 12 (1 bit)

LPHFPE : LPHFPE
bits : 13 - 13 (1 bit)

FBTAAE : FBTAAE
bits : 14 - 14 (1 bit)

LPCE : LPCE
bits : 15 - 15 (1 bit)

PGE : PGE
bits : 16 - 16 (1 bit)

PGM : PGM
bits : 20 - 20 (1 bit)

PGO : PGO
bits : 24 - 24 (1 bit)


DSI_VPCR

DSI Host video packet configuration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VPCR DSI_VPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPSIZE

VPSIZE : VPSIZE
bits : 0 - 13 (14 bit)


DSI_CR

DSI Host control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CR DSI_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : EN
bits : 0 - 0 (1 bit)


DSI_VCCR

DSI Host video chunks configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VCCR DSI_VCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUMC

NUMC : NUMC
bits : 0 - 12 (13 bit)


DSI_WCFGR

DSI wrapper configuration register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WCFGR DSI_WCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSIM COLMUX TESRC TEPOL AR VSPOL

DSIM : DSIM
bits : 0 - 0 (1 bit)

COLMUX : COLMUX
bits : 1 - 3 (3 bit)

TESRC : TESRC
bits : 4 - 4 (1 bit)

TEPOL : TEPOL
bits : 5 - 5 (1 bit)

AR : AR
bits : 6 - 6 (1 bit)

VSPOL : VSPOL
bits : 7 - 7 (1 bit)


DSI_WCR

DSI wrapper control register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WCR DSI_WCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLM SHTDN LTDCEN DSIEN

COLM : COLM
bits : 0 - 0 (1 bit)

SHTDN : SHTDN
bits : 1 - 1 (1 bit)

LTDCEN : LTDCEN
bits : 2 - 2 (1 bit)

DSIEN : DSIEN
bits : 3 - 3 (1 bit)


DSI_WIER

DSI wrapper interrupt enable register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WIER DSI_WIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIE ERIE PLLLIE PLLUIE RRIE

TEIE : TEIE
bits : 0 - 0 (1 bit)

ERIE : ERIE
bits : 1 - 1 (1 bit)

PLLLIE : PLLLIE
bits : 9 - 9 (1 bit)

PLLUIE : PLLUIE
bits : 10 - 10 (1 bit)

RRIE : RRIE
bits : 13 - 13 (1 bit)


DSI_WISR

DSI wrapper interrupt and status register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_WISR DSI_WISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIF ERIF BUSY PLLLS PLLLIF PLLUIF RRS RRIF

TEIF : TEIF
bits : 0 - 0 (1 bit)

ERIF : ERIF
bits : 1 - 1 (1 bit)

BUSY : BUSY
bits : 2 - 2 (1 bit)

PLLLS : PLLLS
bits : 8 - 8 (1 bit)

PLLLIF : PLLLIF
bits : 9 - 9 (1 bit)

PLLUIF : PLLUIF
bits : 10 - 10 (1 bit)

RRS : RRS
bits : 12 - 12 (1 bit)

RRIF : RRIF
bits : 13 - 13 (1 bit)


DSI_WIFCR

DSI wrapper interrupt flag clear register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DSI_WIFCR DSI_WIFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEIF CERIF CPLLLIF CPLLUIF CRRIF

CTEIF : CTEIF
bits : 0 - 0 (1 bit)

CERIF : CERIF
bits : 1 - 1 (1 bit)

CPLLLIF : CPLLLIF
bits : 9 - 9 (1 bit)

CPLLUIF : CPLLUIF
bits : 10 - 10 (1 bit)

CRRIF : CRRIF
bits : 13 - 13 (1 bit)


DSI_WPCR0

DSI wrapper PHY configuration register 0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR0 DSI_WPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIX4 SWCL SWDL0 SWDL1 HSICL HSIDL0 HSIDL1 FTXSMCL FTXSMDL CDOFFDL TDDL PDEN TCLKPREPEN TCLKZEROEN THSPREPEN THSTRAILEN THSZEROEN TLPXDEN THSEXITEN TLPXCEN TCLKPOSTEN

UIX4 : UIX4
bits : 0 - 5 (6 bit)

SWCL : SWCL
bits : 6 - 6 (1 bit)

SWDL0 : SWDL0
bits : 7 - 7 (1 bit)

SWDL1 : SWDL1
bits : 8 - 8 (1 bit)

HSICL : HSICL
bits : 9 - 9 (1 bit)

HSIDL0 : HSIDL0
bits : 10 - 10 (1 bit)

HSIDL1 : HSIDL1
bits : 11 - 11 (1 bit)

FTXSMCL : FTXSMCL
bits : 12 - 12 (1 bit)

FTXSMDL : FTXSMDL
bits : 13 - 13 (1 bit)

CDOFFDL : CDOFFDL
bits : 14 - 14 (1 bit)

TDDL : TDDL
bits : 16 - 16 (1 bit)

PDEN : Pull-down enable
bits : 18 - 18 (1 bit)

TCLKPREPEN : Custom time for tCLK-PREPARE enable
bits : 19 - 19 (1 bit)

TCLKZEROEN : Custom time for tCLK-ZERO enable
bits : 20 - 20 (1 bit)

THSPREPEN : Custom time for tHS-PREPARE enable
bits : 21 - 21 (1 bit)

THSTRAILEN : Custom time for tHS-TRAIL enable
bits : 22 - 22 (1 bit)

THSZEROEN : Custom time for tHS-ZERO enable
bits : 23 - 23 (1 bit)

TLPXDEN : Custom time for tLPX for data lanes enable
bits : 24 - 24 (1 bit)

THSEXITEN : Custom time for tHS-EXIT enable
bits : 25 - 25 (1 bit)

TLPXCEN : Custom time for tLPX for clock lane enable
bits : 26 - 26 (1 bit)

TCLKPOSTEN : Custom time for tCLK-POST enable
bits : 27 - 27 (1 bit)


DSI_WPCR1

This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR1 DSI_WPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSTXDCL HSTXDDL LPSRCCL LPSRCDL SDDC HSTXSRCCL HSTXSRCDL FLPRXLPM LPRXFT

HSTXDCL : High-speed transmission delay on clock lane
bits : 0 - 1 (2 bit)

HSTXDDL : High-speed transmission delay on data lanes
bits : 2 - 3 (2 bit)

LPSRCCL : Low-power transmission slew-rate compensation on clock lane
bits : 6 - 7 (2 bit)

LPSRCDL : Low-power transmission slew-rate compensation on data lanes
bits : 8 - 9 (2 bit)

SDDC : SDD control
bits : 12 - 12 (1 bit)

HSTXSRCCL : High-speed transmission slew-rate control on clock lane
bits : 16 - 17 (2 bit)

HSTXSRCDL : High-speed transmission slew-rate control on data lanes
bits : 18 - 19 (2 bit)

FLPRXLPM : Forces LP receiver in low-power mode
bits : 22 - 22 (1 bit)

LPRXFT : Low-power RX low-pass filtering tuning
bits : 25 - 26 (2 bit)


DSI_WPCR2

DSI wrapper PHY configuration register 2
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR2 DSI_WPCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCLKPREP TCLKZERO THSPREP THSTRAIL

TCLKPREP : TCLKPREP
bits : 0 - 7 (8 bit)

TCLKZERO : TCLKZERO
bits : 8 - 15 (8 bit)

THSPREP : THSPREP
bits : 16 - 23 (8 bit)

THSTRAIL : THSTRAIL
bits : 24 - 31 (8 bit)


DSI_WPCR3

DSI wrapper PHY configuration register 3
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR3 DSI_WPCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THSZERO TLPXD THSEXIT TLPXC

THSZERO : THSZERO
bits : 0 - 7 (8 bit)

TLPXD : TLPXD
bits : 8 - 15 (8 bit)

THSEXIT : THSEXIT
bits : 16 - 23 (8 bit)

TLPXC : TLPXC
bits : 24 - 31 (8 bit)


DSI_WPCR4

DSI wrapper PHY configuration register 4
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR4 DSI_WPCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCLKPOST

TCLKPOST : TCLKPOST
bits : 0 - 7 (8 bit)


DSI_WRPCR

DSI wrapper regulator and PLL control register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WRPCR DSI_WRPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLEN NDIV IDF ODF REGEN

PLLEN : PLLEN
bits : 0 - 0 (1 bit)

NDIV : NDIV
bits : 2 - 8 (7 bit)

IDF : IDF
bits : 11 - 14 (4 bit)

ODF : ODF
bits : 16 - 17 (2 bit)

REGEN : REGEN
bits : 24 - 24 (1 bit)


DSI_VNPCR

DSI Host video null packet configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VNPCR DSI_VNPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPSIZE

NPSIZE : NPSIZE
bits : 0 - 12 (13 bit)


DSI_VHSACR

DSI Host video HSA configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VHSACR DSI_VHSACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSA

HSA : HSA
bits : 0 - 11 (12 bit)


DSI_VHBPCR

DSI Host video HBP configuration register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VHBPCR DSI_VHBPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBP

HBP : HBP
bits : 0 - 11 (12 bit)


DSI_VLCR

DSI Host video line configuration register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VLCR DSI_VLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLINE

HLINE : HLINE
bits : 0 - 14 (15 bit)


DSI_VVSACR

DSI Host video VSA configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVSACR DSI_VVSACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSA

VSA : VSA
bits : 0 - 9 (10 bit)


DSI_VVBPCR

DSI Host video VBP configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVBPCR DSI_VVBPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBP

VBP : VBP
bits : 0 - 9 (10 bit)


DSI_VVFPCR

DSI Host video VFP configuration register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVFPCR DSI_VVFPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFP

VFP : VFP
bits : 0 - 9 (10 bit)


DSI_VVACR

DSI Host video VA configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVACR DSI_VVACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VA

VA : VA
bits : 0 - 13 (14 bit)


DSI_LCCR

DSI Host LTDC command configuration register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCCR DSI_LCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDSIZE

CMDSIZE : CMDSIZE
bits : 0 - 15 (16 bit)


DSI_CMCR

DSI Host command mode configuration register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CMCR DSI_CMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEARE ARE GSW0TX GSW1TX GSW2TX GSR0TX GSR1TX GSR2TX GLWTX DSW0TX DSW1TX DSR0TX DLWTX MRDPS

TEARE : TEARE
bits : 0 - 0 (1 bit)

ARE : ARE
bits : 1 - 1 (1 bit)

GSW0TX : GSW0TX
bits : 8 - 8 (1 bit)

GSW1TX : GSW1TX
bits : 9 - 9 (1 bit)

GSW2TX : GSW2TX
bits : 10 - 10 (1 bit)

GSR0TX : GSR0TX
bits : 11 - 11 (1 bit)

GSR1TX : GSR1TX
bits : 12 - 12 (1 bit)

GSR2TX : GSR2TX
bits : 13 - 13 (1 bit)

GLWTX : GLWTX
bits : 14 - 14 (1 bit)

DSW0TX : DSW0TX
bits : 16 - 16 (1 bit)

DSW1TX : DSW1TX
bits : 17 - 17 (1 bit)

DSR0TX : DSR0TX
bits : 18 - 18 (1 bit)

DLWTX : DLWTX
bits : 19 - 19 (1 bit)

MRDPS : MRDPS
bits : 24 - 24 (1 bit)


DSI_GHCR

DSI Host generic header configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_GHCR DSI_GHCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT VCID WCLSB WCMSB

DT : DT
bits : 0 - 5 (6 bit)

VCID : VCID
bits : 6 - 7 (2 bit)

WCLSB : WCLSB
bits : 8 - 15 (8 bit)

WCMSB : WCMSB
bits : 16 - 23 (8 bit)


DSI_GPDR

DSI Host generic payload data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_GPDR DSI_GPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1 DATA2 DATA3 DATA4

DATA1 : DATA1
bits : 0 - 7 (8 bit)

DATA2 : DATA2
bits : 8 - 15 (8 bit)

DATA3 : DATA3
bits : 16 - 23 (8 bit)

DATA4 : DATA4
bits : 24 - 31 (8 bit)


DSI_GPSR

DSI Host generic packet status register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_GPSR DSI_GPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDFE CMDFF PWRFE PWRFF PRDFE PRDFF RCB

CMDFE : CMDFE
bits : 0 - 0 (1 bit)

CMDFF : CMDFF
bits : 1 - 1 (1 bit)

PWRFE : PWRFE
bits : 2 - 2 (1 bit)

PWRFF : PWRFF
bits : 3 - 3 (1 bit)

PRDFE : PRDFE
bits : 4 - 4 (1 bit)

PRDFF : PRDFF
bits : 5 - 5 (1 bit)

RCB : RCB
bits : 6 - 6 (1 bit)


DSI_TCCR0

DSI Host timeout counter configuration register 0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR0 DSI_TCCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPRX_TOCNT HSTX_TOCNT

LPRX_TOCNT : LPRX_TOCNT
bits : 0 - 15 (16 bit)

HSTX_TOCNT : HSTX_TOCNT
bits : 16 - 31 (16 bit)


DSI_TCCR1

DSI Host timeout counter configuration register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR1 DSI_TCCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSRD_TOCNT

HSRD_TOCNT : HSRD_TOCNT
bits : 0 - 15 (16 bit)


DSI_CCR

DSI Host clock control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CCR DSI_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXECKDIV TOCKDIV

TXECKDIV : TXECKDIV
bits : 0 - 7 (8 bit)

TOCKDIV : TOCKDIV
bits : 8 - 15 (8 bit)


DSI_TCCR2

DSI Host timeout counter configuration register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR2 DSI_TCCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPRD_TOCNT

LPRD_TOCNT : LPRD_TOCNT
bits : 0 - 15 (16 bit)


DSI_TCCR3

DSI Host timeout counter configuration register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR3 DSI_TCCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSWR_TOCNT PM

HSWR_TOCNT : HSWR_TOCNT
bits : 0 - 15 (16 bit)

PM : PM
bits : 24 - 24 (1 bit)


DSI_TCCR4

DSI Host timeout counter configuration register 4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR4 DSI_TCCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPWR_TOCNT

LPWR_TOCNT : LPWR_TOCNT
bits : 0 - 15 (16 bit)


DSI_TCCR5

DSI Host timeout counter configuration register 5
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR5 DSI_TCCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTA_TOCNT

BTA_TOCNT : BTA_TOCNT
bits : 0 - 15 (16 bit)


DSI_CLCR

DSI Host clock lane configuration register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CLCR DSI_CLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPCC ACR

DPCC : DPCC
bits : 0 - 0 (1 bit)

ACR : ACR
bits : 1 - 1 (1 bit)


DSI_CLTCR

DSI Host clock lane timer configuration register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CLTCR DSI_CLTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LP2HS_TIME HS2LP_TIME

LP2HS_TIME : LP2HS_TIME
bits : 0 - 9 (10 bit)

HS2LP_TIME : HS2LP_TIME
bits : 16 - 25 (10 bit)


DSI_DLTCR

DSI Host data lane timer configuration register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_DLTCR DSI_DLTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRD_TIME LP2HS_TIME HS2LP_TIME

MRD_TIME : Maximum read time
bits : 0 - 14 (15 bit)

LP2HS_TIME : LP2HS_TIME
bits : 16 - 23 (8 bit)

HS2LP_TIME : HS2LP_TIME
bits : 24 - 31 (8 bit)


DSI_PCTLR

DSI Host PHY control register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCTLR DSI_PCTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN CKE

DEN : DEN
bits : 1 - 1 (1 bit)

CKE : CKE
bits : 2 - 2 (1 bit)


DSI_PCONFR

DSI Host PHY configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCONFR DSI_PCONFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NL SW_TIME

NL : NL
bits : 0 - 1 (2 bit)

SW_TIME : SW_TIME
bits : 8 - 15 (8 bit)


DSI_PUCR

DSI Host PHY ULPS control register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PUCR DSI_PUCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 URCL UECL URDL UEDL

URCL : URCL
bits : 0 - 0 (1 bit)

UECL : UECL
bits : 1 - 1 (1 bit)

URDL : URDL
bits : 2 - 2 (1 bit)

UEDL : UEDL
bits : 3 - 3 (1 bit)


DSI_PTTCR

DSI Host PHY TX triggers configuration register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PTTCR DSI_PTTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_TRIG

TX_TRIG : TX_TRIG
bits : 0 - 3 (4 bit)


DSI_PSR

DSI Host PHY status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_PSR DSI_PSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD PSSC UANC PSS0 UAN0 RUE0 PSS1 UAN1

PD : PD
bits : 1 - 1 (1 bit)

PSSC : PSSC
bits : 2 - 2 (1 bit)

UANC : UANC
bits : 3 - 3 (1 bit)

PSS0 : PSS0
bits : 4 - 4 (1 bit)

UAN0 : UAN0
bits : 5 - 5 (1 bit)

RUE0 : RUE0
bits : 6 - 6 (1 bit)

PSS1 : PSS1
bits : 7 - 7 (1 bit)

UAN1 : UAN1
bits : 8 - 8 (1 bit)


DSI_ISR0

DSI Host interrupt and status register 0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_ISR0 DSI_ISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AE0 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 PE0 PE1 PE2 PE3 PE4

AE0 : AE0
bits : 0 - 0 (1 bit)

AE1 : AE1
bits : 1 - 1 (1 bit)

AE2 : AE2
bits : 2 - 2 (1 bit)

AE3 : AE3
bits : 3 - 3 (1 bit)

AE4 : AE4
bits : 4 - 4 (1 bit)

AE5 : AE5
bits : 5 - 5 (1 bit)

AE6 : AE6
bits : 6 - 6 (1 bit)

AE7 : AE7
bits : 7 - 7 (1 bit)

AE8 : AE8
bits : 8 - 8 (1 bit)

AE9 : AE9
bits : 9 - 9 (1 bit)

AE10 : AE10
bits : 10 - 10 (1 bit)

AE11 : AE11
bits : 11 - 11 (1 bit)

AE12 : AE12
bits : 12 - 12 (1 bit)

AE13 : AE13
bits : 13 - 13 (1 bit)

AE14 : AE14
bits : 14 - 14 (1 bit)

AE15 : AE15
bits : 15 - 15 (1 bit)

PE0 : PE0
bits : 16 - 16 (1 bit)

PE1 : PE1
bits : 17 - 17 (1 bit)

PE2 : PE2
bits : 18 - 18 (1 bit)

PE3 : PE3
bits : 19 - 19 (1 bit)

PE4 : PE4
bits : 20 - 20 (1 bit)


DSI_LVCIDR

DSI Host LTDC VCID register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LVCIDR DSI_LVCIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : VCID
bits : 0 - 1 (2 bit)


DSI_ISR1

DSI Host interrupt and status register 1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_ISR1 DSI_ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOHSTX TOLPRX ECCSE ECCME CRCE PSE EOTPE LPWRE GCWRE GPWRE GPTXE GPRDE GPRXE

TOHSTX : TOHSTX
bits : 0 - 0 (1 bit)

TOLPRX : TOLPRX
bits : 1 - 1 (1 bit)

ECCSE : ECCSE
bits : 2 - 2 (1 bit)

ECCME : ECCME
bits : 3 - 3 (1 bit)

CRCE : CRCE
bits : 4 - 4 (1 bit)

PSE : PSE
bits : 5 - 5 (1 bit)

EOTPE : EOTPE
bits : 6 - 6 (1 bit)

LPWRE : LPWRE
bits : 7 - 7 (1 bit)

GCWRE : GCWRE
bits : 8 - 8 (1 bit)

GPWRE : GPWRE
bits : 9 - 9 (1 bit)

GPTXE : GPTXE
bits : 10 - 10 (1 bit)

GPRDE : GPRDE
bits : 11 - 11 (1 bit)

GPRXE : GPRXE
bits : 12 - 12 (1 bit)


DSI_IER0

DSI Host interrupt enable register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_IER0 DSI_IER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AE0IE AE1IE AE2IE AE3IE AE4IE AE5IE AE6IE AE7IE AE8IE AE9IE AE10IE AE11IE AE12IE AE13IE AE14IE AE15IE PE0IE PE1IE PE2IE PE3IE PE4IE

AE0IE : AE0IE
bits : 0 - 0 (1 bit)

AE1IE : AE1IE
bits : 1 - 1 (1 bit)

AE2IE : AE2IE
bits : 2 - 2 (1 bit)

AE3IE : AE3IE
bits : 3 - 3 (1 bit)

AE4IE : AE4IE
bits : 4 - 4 (1 bit)

AE5IE : AE5IE
bits : 5 - 5 (1 bit)

AE6IE : AE6IE
bits : 6 - 6 (1 bit)

AE7IE : AE7IE
bits : 7 - 7 (1 bit)

AE8IE : AE8IE
bits : 8 - 8 (1 bit)

AE9IE : AE9IE
bits : 9 - 9 (1 bit)

AE10IE : AE10IE
bits : 10 - 10 (1 bit)

AE11IE : AE11IE
bits : 11 - 11 (1 bit)

AE12IE : AE12IE
bits : 12 - 12 (1 bit)

AE13IE : AE13IE
bits : 13 - 13 (1 bit)

AE14IE : AE14IE
bits : 14 - 14 (1 bit)

AE15IE : AE15IE
bits : 15 - 15 (1 bit)

PE0IE : PE0IE
bits : 16 - 16 (1 bit)

PE1IE : PE1IE
bits : 17 - 17 (1 bit)

PE2IE : PE2IE
bits : 18 - 18 (1 bit)

PE3IE : PE3IE
bits : 19 - 19 (1 bit)

PE4IE : PE4IE
bits : 20 - 20 (1 bit)


DSI_IER1

DSI Host interrupt enable register 1
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_IER1 DSI_IER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOHSTXIE TOLPRXIE ECCSEIE ECCMEIE CRCEIE PSEIE EOTPEIE LPWREIE GCWREIE GPWREIE GPTXEIE GPRDEIE GPRXEIE

TOHSTXIE : TOHSTXIE
bits : 0 - 0 (1 bit)

TOLPRXIE : TOLPRXIE
bits : 1 - 1 (1 bit)

ECCSEIE : ECCSEIE
bits : 2 - 2 (1 bit)

ECCMEIE : ECCMEIE
bits : 3 - 3 (1 bit)

CRCEIE : CRCEIE
bits : 4 - 4 (1 bit)

PSEIE : PSEIE
bits : 5 - 5 (1 bit)

EOTPEIE : EOTPEIE
bits : 6 - 6 (1 bit)

LPWREIE : LPWREIE
bits : 7 - 7 (1 bit)

GCWREIE : GCWREIE
bits : 8 - 8 (1 bit)

GPWREIE : GPWREIE
bits : 9 - 9 (1 bit)

GPTXEIE : GPTXEIE
bits : 10 - 10 (1 bit)

GPRDEIE : GPRDEIE
bits : 11 - 11 (1 bit)

GPRXEIE : GPRXEIE
bits : 12 - 12 (1 bit)


DSI_FIR0

DSI Host force interrupt register 0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DSI_FIR0 DSI_FIR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAE0 FAE1 FAE2 FAE3 FAE4 FAE5 FAE6 FAE7 FAE8 FAE9 FAE10 FAE11 FAE12 FAE13 FAE14 FAE15 FPE0 FPE1 FPE2 FPE3 FPE4

FAE0 : FAE0
bits : 0 - 0 (1 bit)

FAE1 : FAE1
bits : 1 - 1 (1 bit)

FAE2 : FAE2
bits : 2 - 2 (1 bit)

FAE3 : FAE3
bits : 3 - 3 (1 bit)

FAE4 : FAE4
bits : 4 - 4 (1 bit)

FAE5 : FAE5
bits : 5 - 5 (1 bit)

FAE6 : FAE6
bits : 6 - 6 (1 bit)

FAE7 : FAE7
bits : 7 - 7 (1 bit)

FAE8 : FAE8
bits : 8 - 8 (1 bit)

FAE9 : FAE9
bits : 9 - 9 (1 bit)

FAE10 : FAE10
bits : 10 - 10 (1 bit)

FAE11 : FAE11
bits : 11 - 11 (1 bit)

FAE12 : FAE12
bits : 12 - 12 (1 bit)

FAE13 : FAE13
bits : 13 - 13 (1 bit)

FAE14 : FAE14
bits : 14 - 14 (1 bit)

FAE15 : FAE15
bits : 15 - 15 (1 bit)

FPE0 : FPE0
bits : 16 - 16 (1 bit)

FPE1 : FPE1
bits : 17 - 17 (1 bit)

FPE2 : FPE2
bits : 18 - 18 (1 bit)

FPE3 : FPE3
bits : 19 - 19 (1 bit)

FPE4 : FPE4
bits : 20 - 20 (1 bit)


DSI_FIR1

DSI Host force interrupt register 1
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DSI_FIR1 DSI_FIR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTOHSTX FTOLPRX FECCSE FECCME FCRCE FPSE FEOTPE FLPWRE FGCWRE FGPWRE FGPTXE FGPRDE FGPRXE

FTOHSTX : FTOHSTX
bits : 0 - 0 (1 bit)

FTOLPRX : FTOLPRX
bits : 1 - 1 (1 bit)

FECCSE : FECCSE
bits : 2 - 2 (1 bit)

FECCME : FECCME
bits : 3 - 3 (1 bit)

FCRCE : FCRCE
bits : 4 - 4 (1 bit)

FPSE : FPSE
bits : 5 - 5 (1 bit)

FEOTPE : FEOTPE
bits : 6 - 6 (1 bit)

FLPWRE : FLPWRE
bits : 7 - 7 (1 bit)

FGCWRE : FGCWRE
bits : 8 - 8 (1 bit)

FGPWRE : FGPWRE
bits : 9 - 9 (1 bit)

FGPTXE : FGPTXE
bits : 10 - 10 (1 bit)

FGPRDE : FGPRDE
bits : 11 - 11 (1 bit)

FGPRXE : FGPRXE
bits : 12 - 12 (1 bit)



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