\n
address_offset : 0x0 Bytes (0x0)
size : 0xD byte (0x0)
mem_usage : registers
protection :
Cache Level ID register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CL1 : CL1
bits : 0 - 2 (3 bit)
CL2 : CL2
bits : 3 - 5 (3 bit)
CL3 : CL3
bits : 6 - 8 (3 bit)
CL4 : CL4
bits : 9 - 11 (3 bit)
CL5 : CL5
bits : 12 - 14 (3 bit)
CL6 : CL6
bits : 15 - 17 (3 bit)
CL7 : CL7
bits : 18 - 20 (3 bit)
LoUIS : LoUIS
bits : 21 - 23 (3 bit)
LoC : LoC
bits : 24 - 26 (3 bit)
LoU : LoU
bits : 27 - 29 (3 bit)
Cache Type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
_IminLine : IminLine
bits : 0 - 3 (4 bit)
DMinLine : DMinLine
bits : 16 - 19 (4 bit)
ERG : ERG
bits : 20 - 23 (4 bit)
CWG : CWG
bits : 24 - 27 (4 bit)
Format : Format
bits : 29 - 31 (3 bit)
Cache Size ID register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LineSize : LineSize
bits : 0 - 2 (3 bit)
Associativity : Associativity
bits : 3 - 12 (10 bit)
NumSets : NumSets
bits : 13 - 27 (15 bit)
WA : WA
bits : 28 - 28 (1 bit)
RA : RA
bits : 29 - 29 (1 bit)
WB : WB
bits : 30 - 30 (1 bit)
WT : WT
bits : 31 - 31 (1 bit)
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