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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD1 byte (0x0)
mem_usage : registers
protection :

Registers

ISR

CFGR2

SMPR1

SMPR2

PCSEL

LTR1

LHTR1

SQR1

SQR2

SQR3

SQR4

IER

DR

JSQR

OFR1

OFR2

OFR3

OFR4

CR

JDR1

JDR2

JDR3

JDR4

AWD2CR

AWD3CR

LTR2

HTR2

LTR3

HTR3

CFGR

DIFSEL

CALFACT

CALFACT2


ISR

ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDY EOSMP EOC EOS OVR JEOC JEOS AWD1 AWD2 AWD3 JQOVF

ADRDY : ADC ready flag
bits : 0 - 0 (1 bit)

EOSMP : ADC group regular end of sampling flag
bits : 1 - 1 (1 bit)

EOC : ADC group regular end of unitary conversion flag
bits : 2 - 2 (1 bit)

EOS : ADC group regular end of sequence conversions flag
bits : 3 - 3 (1 bit)

OVR : ADC group regular overrun flag
bits : 4 - 4 (1 bit)

JEOC : ADC group injected end of unitary conversion flag
bits : 5 - 5 (1 bit)

JEOS : ADC group injected end of sequence conversions flag
bits : 6 - 6 (1 bit)

AWD1 : ADC analog watchdog 1 flag
bits : 7 - 7 (1 bit)

AWD2 : ADC analog watchdog 2 flag
bits : 8 - 8 (1 bit)

AWD3 : ADC analog watchdog 3 flag
bits : 9 - 9 (1 bit)

JQOVF : ADC group injected contexts queue overflow flag
bits : 10 - 10 (1 bit)


CFGR2

ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROVSE JOVSE OVSS TROVS ROVSM RSHIFT1 RSHIFT2 RSHIFT3 RSHIFT4 OSR LSHIFT

ROVSE : ADC oversampler enable on scope ADC group regular
bits : 0 - 0 (1 bit)

JOVSE : ADC oversampler enable on scope ADC group injected
bits : 1 - 1 (1 bit)

OVSS : ADC oversampling shift
bits : 5 - 8 (4 bit)

TROVS : ADC oversampling discontinuous mode (triggered mode) for ADC group regular
bits : 9 - 9 (1 bit)

ROVSM : Regular Oversampling mode
bits : 10 - 10 (1 bit)

RSHIFT1 : Right-shift data after Offset 1 correction
bits : 11 - 11 (1 bit)

RSHIFT2 : Right-shift data after Offset 2 correction
bits : 12 - 12 (1 bit)

RSHIFT3 : Right-shift data after Offset 3 correction
bits : 13 - 13 (1 bit)

RSHIFT4 : Right-shift data after Offset 4 correction
bits : 14 - 14 (1 bit)

OSR : Oversampling ratio
bits : 16 - 25 (10 bit)

LSHIFT : Left shift factor
bits : 28 - 31 (4 bit)


SMPR1

ADC sampling time register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR1 SMPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP1 SMP2 SMP3 SMP4 SMP5 SMP6 SMP7 SMP8 SMP9

SMP1 : ADC channel 1 sampling time selection
bits : 3 - 5 (3 bit)

SMP2 : ADC channel 2 sampling time selection
bits : 6 - 8 (3 bit)

SMP3 : ADC channel 3 sampling time selection
bits : 9 - 11 (3 bit)

SMP4 : ADC channel 4 sampling time selection
bits : 12 - 14 (3 bit)

SMP5 : ADC channel 5 sampling time selection
bits : 15 - 17 (3 bit)

SMP6 : ADC channel 6 sampling time selection
bits : 18 - 20 (3 bit)

SMP7 : ADC channel 7 sampling time selection
bits : 21 - 23 (3 bit)

SMP8 : ADC channel 8 sampling time selection
bits : 24 - 26 (3 bit)

SMP9 : ADC channel 9 sampling time selection
bits : 27 - 29 (3 bit)


SMPR2

ADC sampling time register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR2 SMPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP10 SMP11 SMP12 SMP13 SMP14 SMP15 SMP16 SMP17 SMP18 SMP19

SMP10 : ADC channel 10 sampling time selection
bits : 0 - 2 (3 bit)

SMP11 : ADC channel 11 sampling time selection
bits : 3 - 5 (3 bit)

SMP12 : ADC channel 12 sampling time selection
bits : 6 - 8 (3 bit)

SMP13 : ADC channel 13 sampling time selection
bits : 9 - 11 (3 bit)

SMP14 : ADC channel 14 sampling time selection
bits : 12 - 14 (3 bit)

SMP15 : ADC channel 15 sampling time selection
bits : 15 - 17 (3 bit)

SMP16 : ADC channel 16 sampling time selection
bits : 18 - 20 (3 bit)

SMP17 : ADC channel 17 sampling time selection
bits : 21 - 23 (3 bit)

SMP18 : ADC channel 18 sampling time selection
bits : 24 - 26 (3 bit)

SMP19 : ADC channel 18 sampling time selection
bits : 27 - 29 (3 bit)


PCSEL

ADC pre channel selection register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCSEL PCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCSEL

PCSEL : Channel x (VINP[i]) pre selection
bits : 0 - 19 (20 bit)


LTR1

ADC analog watchdog 1 threshold register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTR1 LTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTR1

LTR1 : ADC analog watchdog 1 threshold low
bits : 0 - 25 (26 bit)


LHTR1

ADC analog watchdog 2 threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LHTR1 LHTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHTR1

LHTR1 : ADC analog watchdog 2 threshold low
bits : 0 - 25 (26 bit)


SQR1

ADC group regular sequencer ranks register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR1 SQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3 SQ1 SQ2 SQ3 SQ4

L3 : L3
bits : 0 - 3 (4 bit)

SQ1 : ADC group regular sequencer rank 1
bits : 6 - 10 (5 bit)

SQ2 : ADC group regular sequencer rank 2
bits : 12 - 16 (5 bit)

SQ3 : ADC group regular sequencer rank 3
bits : 18 - 22 (5 bit)

SQ4 : ADC group regular sequencer rank 4
bits : 24 - 28 (5 bit)


SQR2

ADC group regular sequencer ranks register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR2 SQR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ5 SQ6 SQ7 SQ8 SQ9

SQ5 : ADC group regular sequencer rank 5
bits : 0 - 4 (5 bit)

SQ6 : ADC group regular sequencer rank 6
bits : 6 - 10 (5 bit)

SQ7 : ADC group regular sequencer rank 7
bits : 12 - 16 (5 bit)

SQ8 : ADC group regular sequencer rank 8
bits : 18 - 22 (5 bit)

SQ9 : ADC group regular sequencer rank 9
bits : 24 - 28 (5 bit)


SQR3

ADC group regular sequencer ranks register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR3 SQR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ10 SQ11 SQ12 SQ13 SQ14

SQ10 : ADC group regular sequencer rank 10
bits : 0 - 4 (5 bit)

SQ11 : ADC group regular sequencer rank 11
bits : 6 - 10 (5 bit)

SQ12 : ADC group regular sequencer rank 12
bits : 12 - 16 (5 bit)

SQ13 : ADC group regular sequencer rank 13
bits : 18 - 22 (5 bit)

SQ14 : ADC group regular sequencer rank 14
bits : 24 - 28 (5 bit)


SQR4

ADC group regular sequencer ranks register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR4 SQR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ15 SQ16

SQ15 : ADC group regular sequencer rank 15
bits : 0 - 4 (5 bit)

SQ16 : ADC group regular sequencer rank 16
bits : 6 - 10 (5 bit)


IER

ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDYIE EOSMPIE EOCIE EOSIE OVRIE JEOCIE JEOSIE AWD1IE AWD2IE AWD3IE JQOVFIE

ADRDYIE : ADC ready interrupt
bits : 0 - 0 (1 bit)

EOSMPIE : ADC group regular end of sampling interrupt
bits : 1 - 1 (1 bit)

EOCIE : ADC group regular end of unitary conversion interrupt
bits : 2 - 2 (1 bit)

EOSIE : ADC group regular end of sequence conversions interrupt
bits : 3 - 3 (1 bit)

OVRIE : ADC group regular overrun interrupt
bits : 4 - 4 (1 bit)

JEOCIE : ADC group injected end of unitary conversion interrupt
bits : 5 - 5 (1 bit)

JEOSIE : ADC group injected end of sequence conversions interrupt
bits : 6 - 6 (1 bit)

AWD1IE : ADC analog watchdog 1 interrupt
bits : 7 - 7 (1 bit)

AWD2IE : ADC analog watchdog 2 interrupt
bits : 8 - 8 (1 bit)

AWD3IE : ADC analog watchdog 3 interrupt
bits : 9 - 9 (1 bit)

JQOVFIE : ADC group injected contexts queue overflow interrupt
bits : 10 - 10 (1 bit)


DR

ADC group regular conversion data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : ADC group regular conversion data
bits : 0 - 15 (16 bit)


JSQR

ADC group injected sequencer register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JSQR JSQR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JL JEXTSEL JEXTEN JSQ1 JSQ2 JSQ3 JSQ4

JL : ADC group injected sequencer scan length
bits : 0 - 1 (2 bit)

JEXTSEL : ADC group injected external trigger source
bits : 2 - 6 (5 bit)

JEXTEN : ADC group injected external trigger polarity
bits : 7 - 8 (2 bit)

JSQ1 : ADC group injected sequencer rank 1
bits : 9 - 13 (5 bit)

JSQ2 : ADC group injected sequencer rank 2
bits : 15 - 19 (5 bit)

JSQ3 : ADC group injected sequencer rank 3
bits : 21 - 25 (5 bit)

JSQ4 : ADC group injected sequencer rank 4
bits : 27 - 31 (5 bit)


OFR1

ADC offset number 1 register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR1 OFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1 OFFSET1_CH SSATE

OFFSET1 : ADC offset number 1 offset level
bits : 0 - 25 (26 bit)

OFFSET1_CH : ADC offset number 1 channel selection
bits : 26 - 30 (5 bit)

SSATE : ADC offset number 1 enable
bits : 31 - 31 (1 bit)


OFR2

ADC offset number 2 register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR2 OFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1 OFFSET1_CH SSATE

OFFSET1 : ADC offset number 1 offset level
bits : 0 - 25 (26 bit)

OFFSET1_CH : ADC offset number 1 channel selection
bits : 26 - 30 (5 bit)

SSATE : ADC offset number 1 enable
bits : 31 - 31 (1 bit)


OFR3

ADC offset number 3 register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR3 OFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1 OFFSET1_CH SSATE

OFFSET1 : ADC offset number 1 offset level
bits : 0 - 25 (26 bit)

OFFSET1_CH : ADC offset number 1 channel selection
bits : 26 - 30 (5 bit)

SSATE : ADC offset number 1 enable
bits : 31 - 31 (1 bit)


OFR4

ADC offset number 4 register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR4 OFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1 OFFSET1_CH SSATE

OFFSET1 : ADC offset number 1 offset level
bits : 0 - 25 (26 bit)

OFFSET1_CH : ADC offset number 1 channel selection
bits : 26 - 30 (5 bit)

SSATE : ADC offset number 1 enable
bits : 31 - 31 (1 bit)


CR

ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADEN ADDIS ADSTART JADSTART ADSTP JADSTP BOOST ADCALLIN LINCALRDYW1 LINCALRDYW2 LINCALRDYW3 LINCALRDYW4 LINCALRDYW5 LINCALRDYW6 ADVREGEN DEEPPWD ADCALDIF ADCAL

ADEN : ADC enable
bits : 0 - 0 (1 bit)

ADDIS : ADC disable
bits : 1 - 1 (1 bit)

ADSTART : ADC group regular conversion start
bits : 2 - 2 (1 bit)

JADSTART : ADC group injected conversion start
bits : 3 - 3 (1 bit)

ADSTP : ADC group regular conversion stop
bits : 4 - 4 (1 bit)

JADSTP : ADC group injected conversion stop
bits : 5 - 5 (1 bit)

BOOST : Boost mode control
bits : 8 - 8 (1 bit)

ADCALLIN : Linearity calibration
bits : 16 - 16 (1 bit)

LINCALRDYW1 : Linearity calibration ready Word 1
bits : 22 - 22 (1 bit)

LINCALRDYW2 : Linearity calibration ready Word 2
bits : 23 - 23 (1 bit)

LINCALRDYW3 : Linearity calibration ready Word 3
bits : 24 - 24 (1 bit)

LINCALRDYW4 : Linearity calibration ready Word 4
bits : 25 - 25 (1 bit)

LINCALRDYW5 : Linearity calibration ready Word 5
bits : 26 - 26 (1 bit)

LINCALRDYW6 : Linearity calibration ready Word 6
bits : 27 - 27 (1 bit)

ADVREGEN : ADC voltage regulator enable
bits : 28 - 28 (1 bit)

DEEPPWD : ADC deep power down enable
bits : 29 - 29 (1 bit)

ADCALDIF : ADC differential mode for calibration
bits : 30 - 30 (1 bit)

ADCAL : ADC calibration
bits : 31 - 31 (1 bit)


JDR1

ADC group injected sequencer rank 1 register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR1 JDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA1

JDATA1 : ADC group injected sequencer rank 1 conversion data
bits : 0 - 31 (32 bit)


JDR2

ADC group injected sequencer rank 2 register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR2 JDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA2

JDATA2 : ADC group injected sequencer rank 2 conversion data
bits : 0 - 31 (32 bit)


JDR3

ADC group injected sequencer rank 3 register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR3 JDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA3

JDATA3 : ADC group injected sequencer rank 3 conversion data
bits : 0 - 31 (32 bit)


JDR4

ADC group injected sequencer rank 4 register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR4 JDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA4

JDATA4 : ADC group injected sequencer rank 4 conversion data
bits : 0 - 31 (32 bit)


AWD2CR

ADC analog watchdog 2 configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD2CR AWD2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD2CH

AWD2CH : ADC analog watchdog 2 monitored channel selection
bits : 0 - 19 (20 bit)


AWD3CR

ADC analog watchdog 3 configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD3CR AWD3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD3CH

AWD3CH : ADC analog watchdog 3 monitored channel selection
bits : 1 - 20 (20 bit)


LTR2

ADC watchdog lower threshold register 2
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTR2 LTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTR2

LTR2 : Analog watchdog 2 lower threshold
bits : 0 - 25 (26 bit)


HTR2

ADC watchdog higher threshold register 2
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HTR2 HTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTR2

HTR2 : Analog watchdog 2 higher threshold
bits : 0 - 25 (26 bit)


LTR3

ADC watchdog lower threshold register 3
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTR3 LTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTR3

LTR3 : Analog watchdog 3 lower threshold
bits : 0 - 25 (26 bit)


HTR3

ADC watchdog higher threshold register 3
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HTR3 HTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTR3

HTR3 : Analog watchdog 3 higher threshold
bits : 0 - 25 (26 bit)


CFGR

ADC configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMNGT RES EXTSEL EXTEN OVRMOD CONT AUTDLY DISCEN DISCNUM JDISCEN JQM AWD1SGL AWD1EN JAWD1EN JAUTO AWDCH1CH JQDIS

DMNGT : ADC DMA transfer enable
bits : 0 - 1 (2 bit)

RES : ADC data resolution
bits : 2 - 4 (3 bit)

EXTSEL : ADC group regular external trigger source
bits : 5 - 9 (5 bit)

EXTEN : ADC group regular external trigger polarity
bits : 10 - 11 (2 bit)

OVRMOD : ADC group regular overrun configuration
bits : 12 - 12 (1 bit)

CONT : ADC group regular continuous conversion mode
bits : 13 - 13 (1 bit)

AUTDLY : ADC low power auto wait
bits : 14 - 14 (1 bit)

DISCEN : ADC group regular sequencer discontinuous mode
bits : 16 - 16 (1 bit)

DISCNUM : ADC group regular sequencer discontinuous number of ranks
bits : 17 - 19 (3 bit)

JDISCEN : ADC group injected sequencer discontinuous mode
bits : 20 - 20 (1 bit)

JQM : ADC group injected contexts queue mode
bits : 21 - 21 (1 bit)

AWD1SGL : ADC analog watchdog 1 monitoring a single channel or all channels
bits : 22 - 22 (1 bit)

AWD1EN : ADC analog watchdog 1 enable on scope ADC group regular
bits : 23 - 23 (1 bit)

JAWD1EN : ADC analog watchdog 1 enable on scope ADC group injected
bits : 24 - 24 (1 bit)

JAUTO : ADC group injected automatic trigger mode
bits : 25 - 25 (1 bit)

AWDCH1CH : ADC analog watchdog 1 monitored channel selection
bits : 26 - 30 (5 bit)

JQDIS : ADC group injected contexts queue disable
bits : 31 - 31 (1 bit)


DIFSEL

ADC channel differential or single-ended mode selection register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIFSEL DIFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIFSEL

DIFSEL : ADC channel differential or single-ended mode for channel
bits : 0 - 19 (20 bit)


CALFACT

ADC calibration factors register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALFACT CALFACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALFACT_S CALFACT_D

CALFACT_S : ADC calibration factor in single-ended mode
bits : 0 - 10 (11 bit)

CALFACT_D : ADC calibration factor in differential mode
bits : 16 - 26 (11 bit)


CALFACT2

ADC Calibration Factor register 2
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALFACT2 CALFACT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINCALFACT

LINCALFACT : Linearity Calibration Factor
bits : 0 - 29 (30 bit)



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