\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
BCR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Memory bank enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bitWREN
bits : 12 - 12 (1 bit)
WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
CPSIZE : CRAM page size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous Clock Enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO Disable
bits : 21 - 21 (1 bit)
BCR3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bit
bits : 12 - 12 (1 bit)
WAITEN : Write enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
CPSIZE : CRAM page size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous Clock Enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO Disable
bits : 21 - 21 (1 bit)
BWTR1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
BWTR2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
BWTR3
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
BWTR4
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
BTR3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio
bits : 20 - 23 (4 bit)
DATLAT : Data latency
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
BCR4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bit
bits : 12 - 12 (1 bit)
WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Extended mode enable
bits : 15 - 15 (1 bit)
CPSIZE : CRAM page size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous Clock Enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO Disable
bits : 21 - 21 (1 bit)
BTR4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio
bits : 20 - 23 (4 bit)
DATLAT : Data latency
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
BTR1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio
bits : 20 - 23 (4 bit)
DATLAT : Data latency
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
BCR2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bit
bits : 12 - 12 (1 bit)
WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
CPSIZE : CRAM page size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous Clock Enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO Disable
bits : 21 - 21 (1 bit)
BTR2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio
bits : 20 - 23 (4 bit)
DATLAT : Data latency
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
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