\n

Ethernet

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

DMAMR

DMACCR

DMACTxCR

DMACRxCR

DMACTxDLAR

DMACRxDLAR

DMACTxDTPR

DMACRxDTPR

DMACTxRLR

DMACRxRLR

DMACIER

DMACRxIWTR

DMACCATxDR

DMACCARxDR

DMACCATxBR

DMACCARxBR

DMACSR

DMACMFCR

DMASBMR

DMAISR

DMADSR


DMAMR

DMA mode register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMR DMAMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR DA TXPR PR INTM

SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write

DA : DMA Tx or Rx Arbitration Scheme
bits : 1 - 1 (1 bit)
access : read-only

TXPR : Transmit priority
bits : 11 - 11 (1 bit)
access : read-only

PR : Priority ratio
bits : 12 - 14 (3 bit)
access : read-only

INTM : Interrupt Mode
bits : 16 - 16 (1 bit)
access : read-write


DMACCR

Channel control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACCR DMACCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSS PBLX8 DSL

MSS : Maximum Segment Size
bits : 0 - 13 (14 bit)

PBLX8 : 8xPBL mode
bits : 16 - 16 (1 bit)

DSL : Descriptor Skip Length
bits : 18 - 20 (3 bit)


DMACTxCR

Channel transmit control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxCR DMACTxCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST OSF TSE TXPBL

ST : Start or Stop Transmission Command
bits : 0 - 0 (1 bit)

OSF : Operate on Second Packet
bits : 4 - 4 (1 bit)

TSE : TCP Segmentation Enabled
bits : 12 - 12 (1 bit)

TXPBL : Transmit Programmable Burst Length
bits : 16 - 21 (6 bit)


DMACRxCR

Channel receive control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxCR DMACRxCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR RBSZ RXPBL RPF

SR : Start or Stop Receive Command
bits : 0 - 0 (1 bit)

RBSZ : Receive Buffer size
bits : 1 - 14 (14 bit)

RXPBL : RXPBL
bits : 16 - 21 (6 bit)

RPF : DMA Rx Channel Packet Flush
bits : 31 - 31 (1 bit)


DMACTxDLAR

Channel Tx descriptor list address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxDLAR DMACTxDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDESLA

TDESLA : Start of Transmit List
bits : 2 - 31 (30 bit)


DMACRxDLAR

Channel Rx descriptor list address register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxDLAR DMACRxDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDESLA

RDESLA : Start of Receive List
bits : 2 - 31 (30 bit)


DMACTxDTPR

Channel Tx descriptor tail pointer register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxDTPR DMACTxDTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDT

TDT : Transmit Descriptor Tail Pointer
bits : 2 - 31 (30 bit)


DMACRxDTPR

Channel Rx descriptor tail pointer register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxDTPR DMACRxDTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDT

RDT : Receive Descriptor Tail Pointer
bits : 2 - 31 (30 bit)


DMACTxRLR

Channel Tx descriptor ring length register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTxRLR DMACTxRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRL

TDRL : Transmit Descriptor Ring Length
bits : 0 - 9 (10 bit)


DMACRxRLR

Channel Rx descriptor ring length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxRLR DMACRxRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRL

RDRL : Receive Descriptor Ring Length
bits : 0 - 9 (10 bit)


DMACIER

Channel interrupt enable register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACIER DMACIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TXSE TBUE RIE RBUE RSE RWTE ETIE ERIE FBEE CDEE AIE NIE

TIE : Transmit Interrupt Enable
bits : 0 - 0 (1 bit)

TXSE : Transmit Stopped Enable
bits : 1 - 1 (1 bit)

TBUE : Transmit Buffer Unavailable Enable
bits : 2 - 2 (1 bit)

RIE : Receive Interrupt Enable
bits : 6 - 6 (1 bit)

RBUE : Receive Buffer Unavailable Enable
bits : 7 - 7 (1 bit)

RSE : Receive Stopped Enable
bits : 8 - 8 (1 bit)

RWTE : Receive Watchdog Timeout Enable
bits : 9 - 9 (1 bit)

ETIE : Early Transmit Interrupt Enable
bits : 10 - 10 (1 bit)

ERIE : Early Receive Interrupt Enable
bits : 11 - 11 (1 bit)

FBEE : Fatal Bus Error Enable
bits : 12 - 12 (1 bit)

CDEE : Context Descriptor Error Enable
bits : 13 - 13 (1 bit)

AIE : Abnormal Interrupt Summary Enable
bits : 14 - 14 (1 bit)

NIE : Normal Interrupt Summary Enable
bits : 15 - 15 (1 bit)


DMACRxIWTR

Channel Rx interrupt watchdog timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACRxIWTR DMACRxIWTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWT

RWT : Receive Interrupt Watchdog Timer Count
bits : 0 - 7 (8 bit)


DMACCATxDR

Channel current application transmit descriptor register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCATxDR DMACCATxDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTDESAPTR

CURTDESAPTR : Application Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)


DMACCARxDR

Channel current application receive descriptor register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCARxDR DMACCARxDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRDESAPTR

CURRDESAPTR : Application Receive Descriptor Address Pointer
bits : 0 - 31 (32 bit)


DMACCATxBR

Channel current application transmit buffer register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCATxBR DMACCATxBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTBUFAPTR

CURTBUFAPTR : Application Transmit Buffer Address Pointer
bits : 0 - 31 (32 bit)


DMACCARxBR

Channel current application receive buffer register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACCARxBR DMACCARxBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRBUFAPTR

CURRBUFAPTR : Application Receive Buffer Address Pointer
bits : 0 - 31 (32 bit)


DMACSR

Channel status register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACSR DMACSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI TPS TBU RI RBU RPS RWT ET ER FBE CDE AIS NIS TEB REB

TI : Transmit Interrupt
bits : 0 - 0 (1 bit)
access : read-write

TPS : Transmit Process Stopped
bits : 1 - 1 (1 bit)
access : read-write

TBU : Transmit Buffer Unavailable
bits : 2 - 2 (1 bit)
access : read-write

RI : Receive Interrupt
bits : 6 - 6 (1 bit)
access : read-write

RBU : Receive Buffer Unavailable
bits : 7 - 7 (1 bit)
access : read-write

RPS : Receive Process Stopped
bits : 8 - 8 (1 bit)
access : read-write

RWT : Receive Watchdog Timeout
bits : 9 - 9 (1 bit)
access : read-write

ET : Early Transmit Interrupt
bits : 10 - 10 (1 bit)
access : read-write

ER : Early Receive Interrupt
bits : 11 - 11 (1 bit)
access : read-write

FBE : Fatal Bus Error
bits : 12 - 12 (1 bit)
access : read-write

CDE : Context Descriptor Error
bits : 13 - 13 (1 bit)
access : read-write

AIS : Abnormal Interrupt Summary
bits : 14 - 14 (1 bit)
access : read-write

NIS : Normal Interrupt Summary
bits : 15 - 15 (1 bit)
access : read-write

TEB : Tx DMA Error Bits
bits : 16 - 18 (3 bit)
access : read-only

REB : Rx DMA Error Bits
bits : 19 - 21 (3 bit)
access : read-only


DMACMFCR

Channel missed frame count register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACMFCR DMACMFCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFC MFCO

MFC : Dropped Packet Counters
bits : 0 - 10 (11 bit)

MFCO : Overflow status of the MFC Counter
bits : 15 - 15 (1 bit)


DMASBMR

System bus mode register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASBMR DMASBMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB AAL MB RB

FB : Fixed Burst Length
bits : 0 - 0 (1 bit)
access : read-write

AAL : Address-Aligned Beats
bits : 12 - 12 (1 bit)
access : read-write

MB : Mixed Burst
bits : 14 - 14 (1 bit)
access : read-only

RB : Rebuild INCRx Burst
bits : 15 - 15 (1 bit)
access : read-only


DMAISR

Interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAISR DMAISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC0IS MTLIS MACIS

DC0IS : DMA Channel Interrupt Status
bits : 0 - 0 (1 bit)

MTLIS : MTL Interrupt Status
bits : 16 - 16 (1 bit)

MACIS : MAC Interrupt Status
bits : 17 - 17 (1 bit)


DMADSR

Debug status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMADSR DMADSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AXWHSTS RPS0 TPS0

AXWHSTS : AHB Master Write Channel
bits : 0 - 0 (1 bit)

RPS0 : DMA Channel Receive Process State
bits : 8 - 11 (4 bit)

TPS0 : DMA Channel Transmit Process State
bits : 12 - 15 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.