\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :
Operating mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTXSTS : DTXSTS
bits : 1 - 1 (1 bit)
CNTPRST : CNTPRST
bits : 8 - 8 (1 bit)
CNTCLR : CNTCLR
bits : 9 - 9 (1 bit)
Tx queue operating mode Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTQ : Flush Transmit Queue
bits : 0 - 0 (1 bit)
access : read-write
TSF : Transmit Store and Forward
bits : 1 - 1 (1 bit)
access : read-write
TXQEN : Transmit Queue Enable
bits : 2 - 3 (2 bit)
access : read-only
TTC : Transmit Threshold Control
bits : 4 - 6 (3 bit)
access : read-write
TQS : Transmit Queue Size
bits : 16 - 18 (3 bit)
access : read-write
Tx queue underflow register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UFFRMCNT : Underflow Packet Counter
bits : 0 - 10 (11 bit)
UFCNTOVF : UFCNTOVF
bits : 11 - 11 (1 bit)
Tx queue debug Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXQPAUSED : TXQPAUSED
bits : 0 - 0 (1 bit)
TRCSTS : TRCSTS
bits : 1 - 2 (2 bit)
TWCSTS : TWCSTS
bits : 3 - 3 (1 bit)
TXQSTS : TXQSTS
bits : 4 - 4 (1 bit)
TXSTSFSTS : TXSTSFSTS
bits : 5 - 5 (1 bit)
PTXQ : PTXQ
bits : 16 - 18 (3 bit)
STXSTSF : STXSTSF
bits : 20 - 22 (3 bit)
Queue interrupt control status Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUNFIS : TXUNFIS
bits : 0 - 0 (1 bit)
TXUIE : TXUIE
bits : 8 - 8 (1 bit)
RXOVFIS : RXOVFIS
bits : 16 - 16 (1 bit)
RXOIE : RXOIE
bits : 24 - 24 (1 bit)
Rx queue operating mode register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : RTC
bits : 0 - 1 (2 bit)
access : read-write
FUP : FUP
bits : 3 - 3 (1 bit)
access : read-write
FEP : FEP
bits : 4 - 4 (1 bit)
access : read-write
RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write
DIS_TCP_EF : DIS_TCP_EF
bits : 6 - 6 (1 bit)
access : read-write
EHFC : EHFC
bits : 7 - 7 (1 bit)
access : read-write
RFA : RFA
bits : 8 - 10 (3 bit)
access : read-write
RFD : RFD
bits : 14 - 16 (3 bit)
access : read-write
RQS : RQS
bits : 20 - 22 (3 bit)
access : read-only
Rx queue missed packet and overflow counter register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVFPKTCNT : OVFPKTCNT
bits : 0 - 10 (11 bit)
OVFCNTOVF : OVFCNTOVF
bits : 11 - 11 (1 bit)
MISPKTCNT : MISPKTCNT
bits : 16 - 26 (11 bit)
MISCNTOVF : MISCNTOVF
bits : 27 - 27 (1 bit)
Rx queue debug register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RWCSTS : RWCSTS
bits : 0 - 0 (1 bit)
RRCSTS : RRCSTS
bits : 1 - 2 (2 bit)
RXQSTS : RXQSTS
bits : 4 - 5 (2 bit)
PRXQ : PRXQ
bits : 16 - 29 (14 bit)
Interrupt status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Q0IS : Queue interrupt status
bits : 0 - 0 (1 bit)
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