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FDCAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CREL

IR

IE

CCFG

CSTAT

CWD


CREL

Clock Calibration Unit Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CREL CREL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY MON YEAR SUBSTEP STEP REL

DAY : Time Stamp Day
bits : 0 - 7 (8 bit)

MON : Time Stamp Month
bits : 8 - 15 (8 bit)

YEAR : Time Stamp Year
bits : 16 - 19 (4 bit)

SUBSTEP : Sub-step of Core Release
bits : 20 - 23 (4 bit)

STEP : Step of Core Release
bits : 24 - 27 (4 bit)

REL : Core Release
bits : 28 - 31 (4 bit)


IR

Clock Calibration Unit Interrupt Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IR IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CWE CSC

CWE : Calibration Watchdog Event
bits : 0 - 0 (1 bit)

CSC : Calibration State Changed
bits : 1 - 1 (1 bit)


IE

Clock Calibration Unit Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CWEE CSCE

CWEE : Calibration Watchdog Event Enable
bits : 0 - 0 (1 bit)

CSCE : Calibration State Changed Enable
bits : 1 - 1 (1 bit)


CCFG

Calibration Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCFG CCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TQBT BCC CFL OCPM CDIV SWR

TQBT : Time Quanta per Bit Time
bits : 0 - 4 (5 bit)

BCC : Bypass Clock Calibration
bits : 6 - 6 (1 bit)

CFL : Calibration Field Length
bits : 7 - 7 (1 bit)

OCPM : Oscillator Clock Periods Minimum
bits : 8 - 15 (8 bit)

CDIV : Clock Divider
bits : 16 - 19 (4 bit)

SWR : Software Reset
bits : 31 - 31 (1 bit)


CSTAT

Calibration Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSTAT CSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCPC TQC CALS

OCPC : Oscillator Clock Period Counter
bits : 0 - 17 (18 bit)

TQC : Time Quanta Counter
bits : 18 - 28 (11 bit)

CALS : Calibration State
bits : 30 - 31 (2 bit)


CWD

Calibration Watchdog Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWD CWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDC WDV

WDC : WDC
bits : 0 - 15 (16 bit)

WDV : WDV
bits : 16 - 31 (16 bit)



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