\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI8 : EXTI x configuration (x = 8 to 11)
bits : 0 - 3 (4 bit)
EXTI9 : EXTI x configuration (x = 8 to 11)
bits : 4 - 7 (4 bit)
EXTI10 : EXTI10
bits : 8 - 11 (4 bit)
EXTI11 : EXTI x configuration (x = 8 to 11)
bits : 12 - 15 (4 bit)
SYSCFG package register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PKG : Package
bits : 0 - 3 (4 bit)
external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI12 : EXTI x configuration (x = 12 to 15)
bits : 0 - 3 (4 bit)
EXTI13 : EXTI x configuration (x = 12 to 15)
bits : 4 - 7 (4 bit)
EXTI14 : EXTI x configuration (x = 12 to 15)
bits : 8 - 11 (4 bit)
EXTI15 : EXTI x configuration (x = 12 to 15)
bits : 12 - 15 (4 bit)
configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM4L : CM4L
bits : 0 - 0 (1 bit)
PVDL : PVDL
bits : 2 - 2 (1 bit)
FLASHL : FLASHL
bits : 3 - 3 (1 bit)
CM7L : CM7L
bits : 6 - 6 (1 bit)
BKRAML : BKRAML
bits : 7 - 7 (1 bit)
SRAM4L : SRAM4L
bits : 9 - 9 (1 bit)
SRAM3L : SRAM3L
bits : 10 - 10 (1 bit)
SRAM2L : SRAM2L
bits : 11 - 11 (1 bit)
SRAM1L : SRAM1L
bits : 12 - 12 (1 bit)
DTCML : DTCML
bits : 13 - 13 (1 bit)
ITCML : ITCML
bits : 14 - 14 (1 bit)
AXISRAML : AXISRAML
bits : 15 - 15 (1 bit)
compensation cell control/status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : enable
bits : 0 - 0 (1 bit)
CS : Code selection
bits : 1 - 1 (1 bit)
READY : Compensation cell ready flag
bits : 8 - 8 (1 bit)
HSLV : High-speed at low-voltage
bits : 16 - 16 (1 bit)
SYSCFG compensation cell value register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NCV : NMOS compensation value
bits : 0 - 3 (4 bit)
PCV : PMOS compensation value
bits : 4 - 7 (4 bit)
SYSCFG compensation cell code register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCC : NMOS compensation code
bits : 0 - 3 (4 bit)
PCC : PMOS compensation code
bits : 4 - 7 (4 bit)
SYSCFG power control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODEN : Overdrive enable
bits : 0 - 0 (1 bit)
SYSCFG user register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BKS : Bank Swap
bits : 0 - 0 (1 bit)
RDP : Readout protection
bits : 16 - 23 (8 bit)
SYSCFG user register 1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCM4 : Boot Cortex-M4
bits : 0 - 0 (1 bit)
BCM7 : Boot Cortex-M7
bits : 16 - 16 (1 bit)
SYSCFG user register 2
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BORH : BOR_LVL Brownout Reset Threshold Level
bits : 0 - 1 (2 bit)
access : read-only
BCM7_ADD0 : Cortex-M7 Boot Address 0
bits : 16 - 31 (16 bit)
access : read-write
SYSCFG user register 3
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCM4_ADD1 : Cortex-M4 Boot Address 0
bits : 0 - 15 (16 bit)
BCM7_ADD1 : Cortex-M7 Boot Address 1
bits : 16 - 31 (16 bit)
SYSCFG user register 4
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCM4_ADD1 : Mass Erase Protected Area Disabled for bank 1
bits : 0 - 15 (16 bit)
access : read-write
MEPAD_1 : Boot Cortex-M4 Address 1
bits : 16 - 16 (1 bit)
access : read-only
SYSCFG user register 5
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MESAD_1 : Mass erase secured area disabled for bank 1
bits : 0 - 0 (1 bit)
WRPS_1 : Write protection for flash bank 1
bits : 16 - 23 (8 bit)
SYSCFG user register 6
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PA_BEG_1 : Protected area start address for bank 1
bits : 0 - 11 (12 bit)
PA_END_1 : Protected area end address for bank 1
bits : 16 - 27 (12 bit)
SYSCFG user register 7
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SA_BEG_1 : Secured area start address for bank 1
bits : 0 - 11 (12 bit)
SA_END_1 : Secured area end address for bank 1
bits : 16 - 27 (12 bit)
SYSCFG user register 8
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MEPAD_2 : Mass erase protected area disabled for bank 2
bits : 0 - 0 (1 bit)
MESAD_2 : Mass erase secured area disabled for bank 2
bits : 16 - 16 (1 bit)
SYSCFG user register 9
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRPS_2 : Write protection for flash bank 2
bits : 0 - 7 (8 bit)
PA_BEG_2 : Protected area start address for bank 2
bits : 16 - 27 (12 bit)
SYSCFG user register 10
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PA_END_2 : Protected area end address for bank 2
bits : 0 - 11 (12 bit)
SA_BEG_2 : Secured area start address for bank 2
bits : 16 - 27 (12 bit)
SYSCFG user register 11
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SA_END_2 : Secured area end address for bank 2
bits : 0 - 11 (12 bit)
IWDG1M : Independent Watchdog 1 mode
bits : 16 - 16 (1 bit)
SYSCFG user register 12
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IWDG2M : Independent Watchdog 2 mode
bits : 0 - 0 (1 bit)
SECURE : Secure mode
bits : 16 - 16 (1 bit)
SYSCFG user register 13
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SDRS : Secured DTCM RAM Size
bits : 0 - 1 (2 bit)
D1SBRST : D1 Standby reset
bits : 16 - 16 (1 bit)
SYSCFG user register 14
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D1STPRST : D1 Stop Reset
bits : 0 - 0 (1 bit)
D2SBRST : D2 Standby Reset
bits : 16 - 16 (1 bit)
SYSCFG user register 15
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D2STPRST : D2 Stop Reset
bits : 0 - 0 (1 bit)
access : read-write
FZIWDGSTB : Freeze independent watchdog in Standby mode
bits : 16 - 16 (1 bit)
access : read-only
SYSCFG user register 16
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FZIWDGSTP : Freeze independent watchdog in Stop mode
bits : 0 - 0 (1 bit)
PKP : Private key programmed
bits : 16 - 16 (1 bit)
SYSCFG user register 17
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IO_HSLV : I/O high speed / low voltage
bits : 0 - 0 (1 bit)
peripheral mode configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C1FMP : I2C1 Fm+
bits : 0 - 0 (1 bit)
I2C2FMP : I2C2 Fm+
bits : 1 - 1 (1 bit)
I2C3FMP : I2C3 Fm+
bits : 2 - 2 (1 bit)
I2C4FMP : I2C4 Fm+
bits : 3 - 3 (1 bit)
PB6FMP : PB(6) Fm+
bits : 4 - 4 (1 bit)
PB7FMP : PB(7) Fast Mode Plus
bits : 5 - 5 (1 bit)
PB8FMP : PB(8) Fast Mode Plus
bits : 6 - 6 (1 bit)
PB9FMP : PB(9) Fm+
bits : 7 - 7 (1 bit)
BOOSTE : Booster Enable
bits : 8 - 8 (1 bit)
BOOSTVDDSEL : Analog switch supply voltage selection
bits : 9 - 9 (1 bit)
EPIS : Ethernet PHY Interface Selection
bits : 21 - 23 (3 bit)
PA0SO : PA0 Switch Open
bits : 24 - 24 (1 bit)
PA1SO : PA1 Switch Open
bits : 25 - 25 (1 bit)
PC2SO : PC2 Switch Open
bits : 26 - 26 (1 bit)
PC3SO : PC3 Switch Open
bits : 27 - 27 (1 bit)
external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0 : EXTI x configuration (x = 0 to 3)
bits : 0 - 3 (4 bit)
EXTI1 : EXTI x configuration (x = 0 to 3)
bits : 4 - 7 (4 bit)
EXTI2 : EXTI x configuration (x = 0 to 3)
bits : 8 - 11 (4 bit)
EXTI3 : EXTI x configuration (x = 0 to 3)
bits : 12 - 15 (4 bit)
external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI4 : EXTI x configuration (x = 4 to 7)
bits : 0 - 3 (4 bit)
EXTI5 : EXTI x configuration (x = 4 to 7)
bits : 4 - 7 (4 bit)
EXTI6 : EXTI x configuration (x = 4 to 7)
bits : 8 - 11 (4 bit)
EXTI7 : EXTI x configuration (x = 4 to 7)
bits : 12 - 15 (4 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.