\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
Access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LATENCY : Read latency
bits : 0 - 2 (3 bit)
WRHIGHFREQ : Flash signal delay
bits : 4 - 5 (2 bit)
FLASH status register for bank 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSY1 : Bank 1 ongoing program flag
bits : 0 - 0 (1 bit)
WBNE1 : Bank 1 write buffer not empty flag
bits : 1 - 1 (1 bit)
QW1 : Bank 1 wait queue flag
bits : 2 - 2 (1 bit)
CRC_BUSY1 : Bank 1 CRC busy flag
bits : 3 - 3 (1 bit)
EOP1 : Bank 1 end-of-program flag
bits : 16 - 16 (1 bit)
WRPERR1 : Bank 1 write protection error flag
bits : 17 - 17 (1 bit)
PGSERR1 : Bank 1 programming sequence error flag
bits : 18 - 18 (1 bit)
STRBERR1 : Bank 1 strobe error flag
bits : 19 - 19 (1 bit)
INCERR1 : Bank 1 inconsistency error flag
bits : 21 - 21 (1 bit)
OPERR1 : Bank 1 write/erase error flag
bits : 22 - 22 (1 bit)
RDPERR1 : Bank 1 read protection error flag
bits : 23 - 23 (1 bit)
RDSERR1 : Bank 1 secure error flag
bits : 24 - 24 (1 bit)
SNECCERR11 : Bank 1 single correction error flag
bits : 25 - 25 (1 bit)
DBECCERR1 : Bank 1 ECC double detection error flag
bits : 26 - 26 (1 bit)
CRCEND1 : Bank 1 CRC-complete flag
bits : 27 - 27 (1 bit)
Access control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LATENCY : Read latency
bits : 0 - 2 (3 bit)
WRHIGHFREQ : Flash signal delay
bits : 4 - 5 (2 bit)
FLASH key register for bank 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
KEYR2 : Bank 2 access configuration unlock key
bits : 0 - 31 (32 bit)
FLASH option key register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPTKEYR : Unlock key option bytes
bits : 0 - 31 (32 bit)
FLASH control register for bank 2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK2 : Bank 2 configuration lock bit
bits : 0 - 0 (1 bit)
PG2 : Bank 2 program enable bit
bits : 1 - 1 (1 bit)
SER2 : Bank 2 sector erase request
bits : 2 - 2 (1 bit)
BER2 : Bank 2 erase request
bits : 3 - 3 (1 bit)
PSIZE2 : Bank 2 program size
bits : 4 - 5 (2 bit)
FW2 : Bank 2 write forcing control bit
bits : 6 - 6 (1 bit)
START2 : Bank 2 bank or sector erase start control bit
bits : 7 - 7 (1 bit)
SNB2 : Bank 2 sector erase selection number
bits : 8 - 10 (3 bit)
CRC_EN : Bank 2 CRC control bit
bits : 15 - 15 (1 bit)
EOPIE2 : Bank 2 end-of-program interrupt control bit
bits : 16 - 16 (1 bit)
WRPERRIE2 : Bank 2 write protection error interrupt enable bit
bits : 17 - 17 (1 bit)
PGSERRIE2 : Bank 2 programming sequence error interrupt enable bit
bits : 18 - 18 (1 bit)
STRBERRIE2 : Bank 2 strobe error interrupt enable bit
bits : 19 - 19 (1 bit)
INCERRIE2 : Bank 2 inconsistency error interrupt enable bit
bits : 21 - 21 (1 bit)
OPERRIE2 : Bank 2 write/erase error interrupt enable bit
bits : 22 - 22 (1 bit)
RDPERRIE2 : Bank 2 read protection error interrupt enable bit
bits : 23 - 23 (1 bit)
RDSERRIE2 : Bank 2 secure error interrupt enable bit
bits : 24 - 24 (1 bit)
SNECCERRIE2 : Bank 2 ECC single correction error interrupt enable bit
bits : 25 - 25 (1 bit)
DBECCERRIE2 : Bank 2 ECC double detection error interrupt enable bit
bits : 26 - 26 (1 bit)
CRCENDIE2 : Bank 2 end of CRC calculation interrupt enable bit
bits : 27 - 27 (1 bit)
FLASH status register for bank 2
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSY2 : Bank 2 ongoing program flag
bits : 0 - 0 (1 bit)
WBNE2 : Bank 2 write buffer not empty flag
bits : 1 - 1 (1 bit)
QW2 : Bank 2 wait queue flag
bits : 2 - 2 (1 bit)
CRC_BUSY2 : Bank 2 CRC busy flag
bits : 3 - 3 (1 bit)
EOP2 : Bank 2 end-of-program flag
bits : 16 - 16 (1 bit)
WRPERR2 : Bank 2 write protection error flag
bits : 17 - 17 (1 bit)
PGSERR2 : Bank 2 programming sequence error flag
bits : 18 - 18 (1 bit)
STRBERR2 : Bank 2 strobe error flag
bits : 19 - 19 (1 bit)
INCERR2 : Bank 2 inconsistency error flag
bits : 21 - 21 (1 bit)
OPERR2 : Bank 2 write/erase error flag
bits : 22 - 22 (1 bit)
RDPERR2 : Bank 2 read protection error flag
bits : 23 - 23 (1 bit)
RDSERR2 : Bank 2 secure error flag
bits : 24 - 24 (1 bit)
SNECCERR2 : Bank 2 single correction error flag
bits : 25 - 25 (1 bit)
DBECCERR2 : Bank 2 ECC double detection error flag
bits : 26 - 26 (1 bit)
CRCEND2 : Bank 2 CRC-complete flag
bits : 27 - 27 (1 bit)
FLASH clear control register for bank 2
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR_EOP2 : Bank 1 EOP1 flag clear bit
bits : 16 - 16 (1 bit)
CLR_WRPERR2 : Bank 2 WRPERR1 flag clear bit
bits : 17 - 17 (1 bit)
CLR_PGSERR2 : Bank 2 PGSERR1 flag clear bi
bits : 18 - 18 (1 bit)
CLR_STRBERR2 : Bank 2 STRBERR1 flag clear bit
bits : 19 - 19 (1 bit)
CLR_INCERR2 : Bank 2 INCERR1 flag clear bit
bits : 21 - 21 (1 bit)
CLR_OPERR2 : Bank 2 OPERR1 flag clear bit
bits : 22 - 22 (1 bit)
CLR_RDPERR2 : Bank 2 RDPERR1 flag clear bit
bits : 23 - 23 (1 bit)
CLR_RDSERR1 : Bank 1 RDSERR1 flag clear bit
bits : 24 - 24 (1 bit)
CLR_SNECCERR2 : Bank 2 SNECCERR1 flag clear bit
bits : 25 - 25 (1 bit)
CLR_DBECCERR1 : Bank 1 DBECCERR1 flag clear bit
bits : 26 - 26 (1 bit)
CLR_CRCEND2 : Bank 2 CRCEND1 flag clear bit
bits : 27 - 27 (1 bit)
FLASH option control register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPTLOCK : FLASH_OPTCR lock option configuration bit
bits : 0 - 0 (1 bit)
OPTSTART : Option byte start change option configuration bit
bits : 1 - 1 (1 bit)
MER : Flash mass erase enable bit
bits : 4 - 4 (1 bit)
OPTCHANGEERRIE : Option byte change error interrupt enable bit
bits : 30 - 30 (1 bit)
SWAP_BANK : Bank swapping configuration bit
bits : 31 - 31 (1 bit)
FLASH option status register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPT_BUSY : Option byte change ongoing flag
bits : 0 - 0 (1 bit)
BOR_LEV : Brownout level option status bit
bits : 2 - 3 (2 bit)
IWDG1_HW : IWDG1 control option status bit
bits : 4 - 4 (1 bit)
nRST_STOP_D1 : D1 DStop entry reset option status bit
bits : 6 - 6 (1 bit)
nRST_STBY_D1 : D1 DStandby entry reset option status bit
bits : 7 - 7 (1 bit)
RDP : Readout protection level option status byte
bits : 8 - 15 (8 bit)
FZ_IWDG_STOP : IWDG Stop mode freeze option status bit
bits : 17 - 17 (1 bit)
FZ_IWDG_SDBY : IWDG Standby mode freeze option status bit
bits : 18 - 18 (1 bit)
ST_RAM_SIZE : DTCM RAM size option status
bits : 19 - 20 (2 bit)
SECURITY : Security enable option status bit
bits : 21 - 21 (1 bit)
RSS1 : User option bit 1
bits : 26 - 26 (1 bit)
PERSO_OK : Device personalization status bit
bits : 28 - 28 (1 bit)
IO_HSLV : I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)
bits : 29 - 29 (1 bit)
OPTCHANGEERR : Option byte change error flag
bits : 30 - 30 (1 bit)
SWAP_BANK_OPT : Bank swapping option status bit
bits : 31 - 31 (1 bit)
FLASH option status register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOR_LEV : BOR reset level option configuration bits
bits : 2 - 3 (2 bit)
IWDG1_HW : IWDG1 option configuration bit
bits : 4 - 4 (1 bit)
nRST_STOP_D1 : Option byte erase after D1 DStop option configuration bit
bits : 6 - 6 (1 bit)
nRST_STBY_D1 : Option byte erase after D1 DStandby option configuration bit
bits : 7 - 7 (1 bit)
RDP : Readout protection level option configuration byte
bits : 8 - 15 (8 bit)
FZ_IWDG_STOP : IWDG Stop mode freeze option configuration bit
bits : 17 - 17 (1 bit)
FZ_IWDG_SDBY : IWDG Standby mode freeze option configuration bit
bits : 18 - 18 (1 bit)
ST_RAM_SIZE : DTCM size select option configuration bits
bits : 19 - 20 (2 bit)
SECURITY : Security option configuration bit
bits : 21 - 21 (1 bit)
RSS1 : User option configuration bit 1
bits : 26 - 26 (1 bit)
RSS2 : User option configuration bit 2
bits : 27 - 27 (1 bit)
IO_HSLV : I/O high-speed at low-voltage (PRODUCT_BELOW_25V)
bits : 29 - 29 (1 bit)
SWAP_BANK_OPT : Bank swapping option configuration bit
bits : 31 - 31 (1 bit)
FLASH option clear control register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR_OPTCHANGEERR : OPTCHANGEERR reset bit
bits : 30 - 30 (1 bit)
FLASH protection address for bank 1
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROT_AREA_START2 : Bank 2 lowest PCROP protected address
bits : 0 - 11 (12 bit)
PROT_AREA_END2 : Bank 2 highest PCROP protected address
bits : 16 - 27 (12 bit)
DMEP2 : Bank 2 PCROP protected erase enable option status bit
bits : 31 - 31 (1 bit)
FLASH secure address for bank 2
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC_AREA_START2 : Bank 2 lowest secure protected address
bits : 0 - 11 (12 bit)
SEC_AREA_END2 : Bank 2 highest secure protected address
bits : 16 - 27 (12 bit)
DMES2 : Bank 2 secure protected erase enable option status bit
bits : 31 - 31 (1 bit)
FLASH secure address for bank 2
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC_AREA_START2 : Bank 2 lowest secure protected address configuration
bits : 0 - 11 (12 bit)
SEC_AREA_END2 : Bank 2 highest secure protected address configuration
bits : 16 - 27 (12 bit)
DMES2 : Bank 2 secure protected erase enable option configuration bit
bits : 31 - 31 (1 bit)
FLASH write sector protection for bank 2
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRPSn2 : Bank 2 sector write protection option status byte
bits : 0 - 7 (8 bit)
FLASH write sector protection for bank 2
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRPSn2 : Bank 2 sector write protection configuration byte
bits : 0 - 7 (8 bit)
FLASH clear control register for bank 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR_EOP1 : Bank 1 EOP1 flag clear bit
bits : 16 - 16 (1 bit)
CLR_WRPERR1 : Bank 1 WRPERR1 flag clear bit
bits : 17 - 17 (1 bit)
CLR_PGSERR1 : Bank 1 PGSERR1 flag clear bi
bits : 18 - 18 (1 bit)
CLR_STRBERR1 : Bank 1 STRBERR1 flag clear bit
bits : 19 - 19 (1 bit)
CLR_INCERR1 : Bank 1 INCERR1 flag clear bit
bits : 21 - 21 (1 bit)
CLR_OPERR1 : Bank 1 OPERR1 flag clear bit
bits : 22 - 22 (1 bit)
CLR_RDPERR1 : Bank 1 RDPERR1 flag clear bit
bits : 23 - 23 (1 bit)
CLR_RDSERR1 : Bank 1 RDSERR1 flag clear bit
bits : 24 - 24 (1 bit)
CLR_SNECCERR1 : Bank 1 SNECCERR1 flag clear bit
bits : 25 - 25 (1 bit)
CLR_DBECCERR1 : Bank 1 DBECCERR1 flag clear bit
bits : 26 - 26 (1 bit)
CLR_CRCEND1 : Bank 1 CRCEND1 flag clear bit
bits : 27 - 27 (1 bit)
FLASH CRC control register for bank 1
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_SECT : Bank 2 CRC sector number
bits : 0 - 2 (3 bit)
ALL_BANK : Bank 2 CRC select bit
bits : 7 - 7 (1 bit)
CRC_BY_SECT : Bank 2 CRC sector mode select bit
bits : 8 - 8 (1 bit)
ADD_SECT : Bank 2 CRC sector select bit
bits : 9 - 9 (1 bit)
CLEAN_SECT : Bank 2 CRC sector list clear bit
bits : 10 - 10 (1 bit)
START_CRC : Bank 2 CRC start bit
bits : 16 - 16 (1 bit)
CLEAN_CRC : Bank 2 CRC clear bit
bits : 17 - 17 (1 bit)
CRC_BURST : Bank 2 CRC burst size
bits : 20 - 21 (2 bit)
FLASH CRC start address register for bank 2
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_START_ADDR : CRC start address on bank 2
bits : 0 - 31 (32 bit)
FLASH CRC end address register for bank 2
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_END_ADDR : CRC end address on bank 2
bits : 0 - 31 (32 bit)
FLASH ECC fail address for bank 2
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FAIL_ECC_ADDR2 : Bank 2 ECC error address
bits : 0 - 14 (15 bit)
FLASH option control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPTLOCK : FLASH_OPTCR lock option configuration bit
bits : 0 - 0 (1 bit)
OPTSTART : Option byte start change option configuration bit
bits : 1 - 1 (1 bit)
MER : Flash mass erase enable bit
bits : 4 - 4 (1 bit)
OPTCHANGEERRIE : Option byte change error interrupt enable bit
bits : 30 - 30 (1 bit)
SWAP_BANK : Bank swapping configuration bit
bits : 31 - 31 (1 bit)
FLASH option status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPT_BUSY : Option byte change ongoing flag
bits : 0 - 0 (1 bit)
BOR_LEV : Brownout level option status bit
bits : 2 - 3 (2 bit)
IWDG1_HW : IWDG1 control option status bit
bits : 4 - 4 (1 bit)
nRST_STOP_D1 : D1 DStop entry reset option status bit
bits : 6 - 6 (1 bit)
nRST_STBY_D1 : D1 DStandby entry reset option status bit
bits : 7 - 7 (1 bit)
RDP : Readout protection level option status byte
bits : 8 - 15 (8 bit)
FZ_IWDG_STOP : IWDG Stop mode freeze option status bit
bits : 17 - 17 (1 bit)
FZ_IWDG_SDBY : IWDG Standby mode freeze option status bit
bits : 18 - 18 (1 bit)
ST_RAM_SIZE : DTCM RAM size option status
bits : 19 - 20 (2 bit)
SECURITY : Security enable option status bit
bits : 21 - 21 (1 bit)
RSS1 : User option bit 1
bits : 26 - 26 (1 bit)
PERSO_OK : Device personalization status bit
bits : 28 - 28 (1 bit)
IO_HSLV : I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)
bits : 29 - 29 (1 bit)
OPTCHANGEERR : Option byte change error flag
bits : 30 - 30 (1 bit)
SWAP_BANK_OPT : Bank swapping option status bit
bits : 31 - 31 (1 bit)
FLASH option status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOR_LEV : BOR reset level option configuration bits
bits : 2 - 3 (2 bit)
IWDG1_HW : IWDG1 option configuration bit
bits : 4 - 4 (1 bit)
nRST_STOP_D1 : Option byte erase after D1 DStop option configuration bit
bits : 6 - 6 (1 bit)
nRST_STBY_D1 : Option byte erase after D1 DStandby option configuration bit
bits : 7 - 7 (1 bit)
RDP : Readout protection level option configuration byte
bits : 8 - 15 (8 bit)
FZ_IWDG_STOP : IWDG Stop mode freeze option configuration bit
bits : 17 - 17 (1 bit)
FZ_IWDG_SDBY : IWDG Standby mode freeze option configuration bit
bits : 18 - 18 (1 bit)
ST_RAM_SIZE : DTCM size select option configuration bits
bits : 19 - 20 (2 bit)
SECURITY : Security option configuration bit
bits : 21 - 21 (1 bit)
RSS1 : User option configuration bit 1
bits : 26 - 26 (1 bit)
RSS2 : User option configuration bit 2
bits : 27 - 27 (1 bit)
IO_HSLV : I/O high-speed at low-voltage (PRODUCT_BELOW_25V)
bits : 29 - 29 (1 bit)
SWAP_BANK_OPT : Bank swapping option configuration bit
bits : 31 - 31 (1 bit)
FLASH option clear control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR_OPTCHANGEERR : OPTCHANGEERR reset bit
bits : 30 - 30 (1 bit)
FLASH protection address for bank 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROT_AREA_START1 : Bank 1 lowest PCROP protected address
bits : 0 - 11 (12 bit)
PROT_AREA_END1 : Bank 1 highest PCROP protected address
bits : 16 - 27 (12 bit)
DMEP1 : Bank 1 PCROP protected erase enable option status bit
bits : 31 - 31 (1 bit)
FLASH protection address for bank 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROT_AREA_START1 : Bank 1 lowest PCROP protected address configuration
bits : 0 - 11 (12 bit)
PROT_AREA_END1 : Bank 1 highest PCROP protected address configuration
bits : 16 - 27 (12 bit)
DMEP1 : Bank 1 PCROP protected erase enable option configuration bit
bits : 31 - 31 (1 bit)
FLASH protection address for bank 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PRAR_PRG1
reset_Mask : 0x0
PROT_AREA_START2 : Bank 2 lowest PCROP protected address configuration
bits : 0 - 11 (12 bit)
PROT_AREA_END2 : Bank 2 highest PCROP protected address configuration
bits : 16 - 27 (12 bit)
DMEP2 : Bank 2 PCROP protected erase enable option configuration bit
bits : 31 - 31 (1 bit)
FLASH secure address for bank 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC_AREA_START1 : Bank 1 lowest secure protected address
bits : 0 - 11 (12 bit)
SEC_AREA_END1 : Bank 1 highest secure protected address
bits : 16 - 27 (12 bit)
DMES1 : Bank 1 secure protected erase enable option status bit
bits : 31 - 31 (1 bit)
FLASH secure address for bank 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC_AREA_START1 : Bank 1 lowest secure protected address configuration
bits : 0 - 11 (12 bit)
SEC_AREA_END1 : Bank 1 highest secure protected address configuration
bits : 16 - 27 (12 bit)
DMES1 : Bank 1 secure protected erase enable option configuration bit
bits : 31 - 31 (1 bit)
FLASH write sector protection for bank 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRPSn1 : Bank 1 sector write protection option status byte
bits : 0 - 7 (8 bit)
FLASH write sector protection for bank 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRPSn1 : Bank 1 sector write protection configuration byte
bits : 0 - 7 (8 bit)
FLASH key register for bank 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYR1 : Bank 1 access configuration unlock key
bits : 0 - 31 (32 bit)
FLASH register with boot address
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOOT_ADD0 : Boot address 0
bits : 0 - 15 (16 bit)
BOOT_ADD1 : Boot address 1
bits : 16 - 31 (16 bit)
FLASH register with boot address
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOOT_ADD0 : Boot address 0
bits : 0 - 15 (16 bit)
BOOT_ADD1 : Boot address 1
bits : 16 - 31 (16 bit)
FLASH CRC control register for bank 1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_SECT : Bank 1 CRC sector number
bits : 0 - 2 (3 bit)
ALL_BANK : Bank 1 CRC select bit
bits : 7 - 7 (1 bit)
CRC_BY_SECT : Bank 1 CRC sector mode select bit
bits : 8 - 8 (1 bit)
ADD_SECT : Bank 1 CRC sector select bit
bits : 9 - 9 (1 bit)
CLEAN_SECT : Bank 1 CRC sector list clear bit
bits : 10 - 10 (1 bit)
START_CRC : Bank 1 CRC start bit
bits : 16 - 16 (1 bit)
CLEAN_CRC : Bank 1 CRC clear bit
bits : 17 - 17 (1 bit)
CRC_BURST : Bank 1 CRC burst size
bits : 20 - 21 (2 bit)
FLASH CRC start address register for bank 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_START_ADDR : CRC start address on bank 1
bits : 0 - 31 (32 bit)
FLASH CRC end address register for bank 1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_END_ADDR : CRC end address on bank 1
bits : 0 - 31 (32 bit)
FLASH CRC data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_DATA : CRC result
bits : 0 - 31 (32 bit)
FLASH ECC fail address for bank 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FAIL_ECC_ADDR1 : Bank 1 ECC error address
bits : 0 - 14 (15 bit)
FLASH option key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPTKEYR : Unlock key option bytes
bits : 0 - 31 (32 bit)
FLASH control register for bank 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK1 : Bank 1 configuration lock bit
bits : 0 - 0 (1 bit)
PG1 : Bank 1 program enable bit
bits : 1 - 1 (1 bit)
SER1 : Bank 1 sector erase request
bits : 2 - 2 (1 bit)
BER1 : Bank 1 erase request
bits : 3 - 3 (1 bit)
PSIZE1 : Bank 1 program size
bits : 4 - 5 (2 bit)
FW1 : Bank 1 write forcing control bit
bits : 6 - 6 (1 bit)
START1 : Bank 1 bank or sector erase start control bit
bits : 7 - 7 (1 bit)
SNB1 : Bank 1 sector erase selection number
bits : 8 - 10 (3 bit)
CRC_EN : Bank 1 CRC control bit
bits : 15 - 15 (1 bit)
EOPIE1 : Bank 1 end-of-program interrupt control bit
bits : 16 - 16 (1 bit)
WRPERRIE1 : Bank 1 write protection error interrupt enable bit
bits : 17 - 17 (1 bit)
PGSERRIE1 : Bank 1 programming sequence error interrupt enable bit
bits : 18 - 18 (1 bit)
STRBERRIE1 : Bank 1 strobe error interrupt enable bit
bits : 19 - 19 (1 bit)
INCERRIE1 : Bank 1 inconsistency error interrupt enable bit
bits : 21 - 21 (1 bit)
OPERRIE1 : Bank 1 write/erase error interrupt enable bit
bits : 22 - 22 (1 bit)
RDPERRIE1 : Bank 1 read protection error interrupt enable bit
bits : 23 - 23 (1 bit)
RDSERRIE1 : Bank 1 secure error interrupt enable bit
bits : 24 - 24 (1 bit)
SNECCERRIE1 : Bank 1 ECC single correction error interrupt enable bit
bits : 25 - 25 (1 bit)
DBECCERRIE1 : Bank 1 ECC double detection error interrupt enable bit
bits : 26 - 26 (1 bit)
CRCENDIE1 : Bank 1 end of CRC calculation interrupt enable bit
bits : 27 - 27 (1 bit)
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