POWER

RESPCMDR

RESP1R

RESP2R

RESP3R

RESP4R

DTIMER

DLENR

DCTRL

DCNTR

STAR

ICR

MASKR

CLKCR

ACKTIMER

IDMACTRLR

IDMABSIZER

IDMABASE0R

IDMABASE1R

ARGR

FIFOR

CMDR

PWRCTRL : SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11.
bits : 0 - 1 (2 bit)

VSWITCH : Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:
bits : 2 - 2 (1 bit)

VSWITCHEN : Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:
bits : 3 - 3 (1 bit)

DIRPOL : Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00).
bits : 4 - 4 (1 bit)

RESPCMD : Response command index
bits : 0 - 5 (6 bit)

CARDSTATUS1 : see Table 432
bits : 0 - 31 (32 bit)

CARDSTATUS2 : see Table404.
bits : 0 - 31 (32 bit)

CARDSTATUS3 : see Table404.
bits : 0 - 31 (32 bit)

CARDSTATUS4 : see Table404.
bits : 0 - 31 (32 bit)

DATATIME : Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods.
bits : 0 - 31 (32 bit)

DATALENGTH : Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0.
bits : 0 - 24 (25 bit)

DTEN : Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards.
bits : 0 - 0 (1 bit)

DTDIR : Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 1 - 1 (1 bit)

DTMODE : Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 2 - 3 (2 bit)

DBLOCKSIZE : Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)
bits : 4 - 7 (4 bit)

RWSTART : Read wait start. If this bit is set, read wait operation starts.
bits : 8 - 8 (1 bit)

RWSTOP : Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state.
bits : 9 - 9 (1 bit)

RWMOD : Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 10 - 10 (1 bit)

SDIOEN : SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation.
bits : 11 - 11 (1 bit)

BOOTACKEN : Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 12 - 12 (1 bit)

FIFORST : FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs.
bits : 13 - 13 (1 bit)

DATACOUNT : Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect.
bits : 0 - 24 (25 bit)

CCRCFAIL : Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 0 - 0 (1 bit)

DCRCFAIL : Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 1 - 1 (1 bit)

CTIMEOUT : Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods.
bits : 2 - 2 (1 bit)

DTIMEOUT : Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 3 - 3 (1 bit)

TXUNDERR : Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 4 - 4 (1 bit)

RXOVERR : Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 5 - 5 (1 bit)

CMDREND : Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 6 - 6 (1 bit)

CMDSENT : Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 7 - 7 (1 bit)

DATAEND : Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 8 - 8 (1 bit)

DHOLD : Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 9 - 9 (1 bit)

DBCKEND : Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 10 - 10 (1 bit)

DABORT : Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 11 - 11 (1 bit)

DPSMACT : Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt.
bits : 12 - 12 (1 bit)

CPSMACT : Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt.
bits : 13 - 13 (1 bit)

TXFIFOHE : Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full.
bits : 14 - 14 (1 bit)

RXFIFOHF : Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty.
bits : 15 - 15 (1 bit)

TXFIFOF : Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty.
bits : 16 - 16 (1 bit)

RXFIFOF : Receive FIFO full This bit is cleared when one FIFO location becomes empty.
bits : 17 - 17 (1 bit)

TXFIFOE : Transmit FIFO empty This bit is cleared when one FIFO location becomes full.
bits : 18 - 18 (1 bit)

RXFIFOE : Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full.
bits : 19 - 19 (1 bit)

BUSYD0 : Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt.
bits : 20 - 20 (1 bit)

BUSYD0END : end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 21 - 21 (1 bit)

SDIOIT : SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 22 - 22 (1 bit)

ACKFAIL : Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 23 - 23 (1 bit)

ACKTIMEOUT : Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 24 - 24 (1 bit)

VSWEND : Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 25 - 25 (1 bit)

CKSTOP : SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 26 - 26 (1 bit)

IDMATE : IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 27 - 27 (1 bit)

IDMABTC : IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.
bits : 28 - 28 (1 bit)

CCRCFAILC : CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag.
bits : 0 - 0 (1 bit)

DCRCFAILC : DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag.
bits : 1 - 1 (1 bit)

CTIMEOUTC : CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag.
bits : 2 - 2 (1 bit)

DTIMEOUTC : DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag.
bits : 3 - 3 (1 bit)

TXUNDERRC : TXUNDERR flag clear bit Set by software to clear TXUNDERR flag.
bits : 4 - 4 (1 bit)

RXOVERRC : RXOVERR flag clear bit Set by software to clear the RXOVERR flag.
bits : 5 - 5 (1 bit)

CMDRENDC : CMDREND flag clear bit Set by software to clear the CMDREND flag.
bits : 6 - 6 (1 bit)

CMDSENTC : CMDSENT flag clear bit Set by software to clear the CMDSENT flag.
bits : 7 - 7 (1 bit)

DATAENDC : DATAEND flag clear bit Set by software to clear the DATAEND flag.
bits : 8 - 8 (1 bit)

DHOLDC : DHOLD flag clear bit Set by software to clear the DHOLD flag.
bits : 9 - 9 (1 bit)

DBCKENDC : DBCKEND flag clear bit Set by software to clear the DBCKEND flag.
bits : 10 - 10 (1 bit)

DABORTC : DABORT flag clear bit Set by software to clear the DABORT flag.
bits : 11 - 11 (1 bit)

BUSYD0ENDC : BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag.
bits : 21 - 21 (1 bit)

SDIOITC : SDIOIT flag clear bit Set by software to clear the SDIOIT flag.
bits : 22 - 22 (1 bit)

ACKFAILC : ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag.
bits : 23 - 23 (1 bit)

ACKTIMEOUTC : ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag.
bits : 24 - 24 (1 bit)

VSWENDC : VSWEND flag clear bit Set by software to clear the VSWEND flag.
bits : 25 - 25 (1 bit)

CKSTOPC : CKSTOP flag clear bit Set by software to clear the CKSTOP flag.
bits : 26 - 26 (1 bit)

IDMATEC : IDMA transfer error clear bit Set by software to clear the IDMATE flag.
bits : 27 - 27 (1 bit)

IDMABTCC : IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag.
bits : 28 - 28 (1 bit)

CCRCFAILIE : Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure.
bits : 0 - 0 (1 bit)

DCRCFAILIE : Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure.
bits : 1 - 1 (1 bit)

CTIMEOUTIE : Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout.
bits : 2 - 2 (1 bit)

DTIMEOUTIE : Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout.
bits : 3 - 3 (1 bit)

TXUNDERRIE : Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.
bits : 4 - 4 (1 bit)

RXOVERRIE : Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
bits : 5 - 5 (1 bit)

CMDRENDIE : Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response.
bits : 6 - 6 (1 bit)

CMDSENTIE : Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command.
bits : 7 - 7 (1 bit)

DATAENDIE : Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end.
bits : 8 - 8 (1 bit)

DHOLDIE : Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state.
bits : 9 - 9 (1 bit)

DBCKENDIE : Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end.
bits : 10 - 10 (1 bit)

DABORTIE : Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted.
bits : 11 - 11 (1 bit)

TXFIFOHEIE : Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.
bits : 14 - 14 (1 bit)

RXFIFOHFIE : Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.
bits : 15 - 15 (1 bit)

RXFIFOFIE : Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full.
bits : 17 - 17 (1 bit)

TXFIFOEIE : Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.
bits : 18 - 18 (1 bit)

BUSYD0ENDIE : BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response.
bits : 21 - 21 (1 bit)

SDIOITIE : SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt.
bits : 22 - 22 (1 bit)

ACKFAILIE : Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail.
bits : 23 - 23 (1 bit)

ACKTIMEOUTIE : Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout.
bits : 24 - 24 (1 bit)

VSWENDIE : Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion.
bits : 25 - 25 (1 bit)

CKSTOPIE : Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped.
bits : 26 - 26 (1 bit)

IDMABTCIE : IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer.
bits : 28 - 28 (1 bit)

CLKDIV : Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc..
bits : 0 - 9 (10 bit)

PWRSAV : Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:
bits : 12 - 12 (1 bit)

WIDBUS : Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)
bits : 14 - 15 (2 bit)

NEGEDGE : SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division and gt 1 (CLKDIV and gt 0) and amp DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) and DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge.
bits : 16 - 16 (1 bit)

HWFC_EN : Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11.
bits : 17 - 17 (1 bit)

DDR : Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS and gt 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division and gt 1. (CLKDIV and gt 0)
bits : 18 - 18 (1 bit)

BUSSPEED : Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)
bits : 19 - 19 (1 bit)

SELCLKRX : Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)
bits : 20 - 21 (2 bit)

ACKTIME : Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods.
bits : 0 - 24 (25 bit)

IDMAEN : IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 0 - 0 (1 bit)

IDMABMODE : Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 1 - 1 (1 bit)

IDMABACT : Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware.
bits : 2 - 2 (1 bit)

IDMABNDT : Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 5 - 12 (8 bit)

IDMABASE0 : Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1).
bits : 0 - 31 (32 bit)

IDMABASE1 : Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0).
bits : 0 - 31 (32 bit)

CMDARG : Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register.
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words.
bits : 0 - 31 (32 bit)

CMDINDEX : Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message.
bits : 0 - 5 (6 bit)

CMDTRANS : The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent.
bits : 6 - 6 (1 bit)

CMDSTOP : The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent.
bits : 7 - 7 (1 bit)

WAITRESP : Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response.
bits : 8 - 9 (2 bit)

WAITINT : CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode.
bits : 10 - 10 (1 bit)

WAITPEND : CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card.
bits : 11 - 11 (1 bit)

CPSMEN : Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0.
bits : 12 - 12 (1 bit)

DTHOLD : Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state.
bits : 13 - 13 (1 bit)

BOOTMODE : Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)
bits : 14 - 14 (1 bit)

BOOTEN : Enable boot mode procedure.
bits : 15 - 15 (1 bit)

CMDSUSPEND : The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1.
bits : 16 - 16 (1 bit)