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DFSDM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CH0CFGR1

CH0DATINR

DFSDM_FLT0CR1 (FLT0CR1)

DFSDM_FLT0CR2 (FLT0CR2)

DFSDM_FLT0ISR (FLT0ISR)

DFSDM_FLT0ICR (FLT0ICR)

DFSDM_FLT0JCHGR (FLT0JCHGR)

DFSDM_FLT0FCR (FLT0FCR)

DFSDM_FLT0JDATAR (FLT0JDATAR)

DFSDM_FLT0RDATAR (FLT0RDATAR)

DFSDM_FLT0AWHTR (FLT0AWHTR)

DFSDM_FLT0AWLTR (FLT0AWLTR)

DFSDM_FLT0AWSR (FLT0AWSR)

DFSDM_FLT0AWCFR (FLT0AWCFR)

DFSDM_FLT0EXMAX (FLT0EXMAX)

DFSDM_FLT0EXMIN (FLT0EXMIN)

DFSDM_FLT0CNVTIMR (FLT0CNVTIMR)

CH0DLYR

DFSDM_FLT1CR1 (FLT1CR1)

DFSDM_FLT1CR2 (FLT1CR2)

DFSDM_FLT1ISR (FLT1ISR)

DFSDM1_ICR (FLT1ICR)

DFSDM_FLT1JCHGR (FLT1CHGR)

DFSDM1_FCR (FLT1FCR)

DFSDM_FLT1JDATAR (FLT1JDATAR)

DFSDM_FLT1RDATAR (FLT1RDATAR)

DFSDM_FLT1AWHTR (FLT1AWHTR)

DFSDM_FLT1AWLTR (FLT1AWLTR)

DFSDM_FLT1AWSR (FLT1AWSR)

DFSDM_FLT1AWCFR (FLT1AWCFR)

DFSDM_FLT1EXMAX (FLT1EXMAX)

DFSDM_FLT1EXMIN (FLT1EXMIN)

DFSDM_FLT1CNVTIMR (FLT1CNVTIMR)

CH1CFGR1

DFSDM_FLT2CR1 (FLT2CR1)

DFSDM_FLT2CR2 (FLT2CR2)

DFSDM_FLT2ISR (FLT2ISR)

DFSDM_FLT2ICR (FLT2ICR)

DFSDM_FLT2JCHGR (FLT2JCHGR)

DFSDM_FLT2FCR (FLT2FCR)

DFSDM_FLT2JDATAR (FLT2JDATAR)

DFSDM_FLT2RDATAR (FLT2RDATAR)

DFSDM_FLT2AWHTR (FLT2AWHTR)

DFSDM_FLT2AWLTR (FLT2AWLTR)

DFSDM_FLT2AWSR (FLT2AWSR)

DFSDM_FLT2AWCFR (FLT2AWCFR)

DFSDM_FLT2EXMAX (FLT2EXMAX)

DFSDM_FLT2EXMIN (FLT2EXMIN)

DFSDM_FLT2CNVTIMR (FLT2CNVTIMR)

CH1CFGR2

CH1AWSCDR

DFSDM_FLT3CR1 (FLT3CR1)

DFSDM_FLT3CR2 (FLT3CR2)

DFSDM_FLT3ISR (FLT3ISR)

DFSDM_FLT3ICR (FLT3ICR)

DFSDM_FLT3JCHGR (FLT3JCHGR)

DFSDM_FLT3FCR (FLT3FCR)

DFSDM_FLT3JDATAR (FLT3JDATAR)

DFSDM_FLT3RDATAR (FLT3RDATAR)

DFSDM_FLT3AWHTR (FLT3AWHTR)

DFSDM_FLT3AWLTR (FLT3AWLTR)

DFSDM_FLT3AWSR (FLT3AWSR)

DFSDM_FLT3AWCFR (FLT3AWCFR)

DFSDM_FLT3EXMAX (FLT3EXMAX)

DFSDM_FLT3EXMIN (FLT3EXMIN)

DFSDM_FLT3CNVTIMR (FLT3CNVTIMR)

CH1WDATR

CH1DATINR

CH1DLYR

CH0CFGR2

CH2CFGR1

CH2CFGR2

CH2AWSCDR

CH2WDATR

CH2DATINR

CH2DLYR

CH3CFGR1

CH3CFGR2

CH3AWSCDR

CH3WDATR

CH3DATINR

CH3DLYR

CH0AWSCDR

CH4CFGR1

CH4CFGR2

CH4AWSCDR

CH4WDATR

CH4DATINR

CH4DLYR

CH5CFGR1

CH5CFGR2

CH5AWSCDR

CH5WDATR

CH5DATINR

CH5DLYR

CH0WDATR

CH6CFGR1

CH6CFGR2

CH6AWSCDR

CH6WDATR

CH6DATINR

CH6DLYR

CH7CFGR1

CH7CFGR2

CH7AWSCDR

CH7WDATR

CH7DATINR

CH7DLYR


CH0CFGR1

channel configuration y register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CFGR1 CH0CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


CH0DATINR

channel data input register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DATINR CH0DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_FLT0CR1 (FLT0CR1)

control register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CR1 DFSDM_FLT0CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM_FLT0CR2 (FLT0CR2)

control register 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CR2 DFSDM_FLT0CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM_FLT0ISR (FLT0ISR)

interrupt and status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0ISR DFSDM_FLT0ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM_FLT0ICR (FLT0ICR)

interrupt flag clear register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0ICR DFSDM_FLT0ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM_FLT0JCHGR (FLT0JCHGR)

injected channel group selection register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0JCHGR DFSDM_FLT0JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM_FLT0FCR (FLT0FCR)

filter control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0FCR DFSDM_FLT0FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)


DFSDM_FLT0JDATAR (FLT0JDATAR)

data register for injected group
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0JDATAR DFSDM_FLT0JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT0RDATAR (FLT0RDATAR)

data register for the regular channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0RDATAR DFSDM_FLT0RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT0AWHTR (FLT0AWHTR)

analog watchdog high threshold register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWHTR DFSDM_FLT0AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT0AWLTR (FLT0AWLTR)

analog watchdog low threshold register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWLTR DFSDM_FLT0AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT0AWSR (FLT0AWSR)

analog watchdog status register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWSR DFSDM_FLT0AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT0AWCFR (FLT0AWCFR)

analog watchdog clear flag register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWCFR DFSDM_FLT0AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT0EXMAX (FLT0EXMAX)

Extremes detector maximum register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0EXMAX DFSDM_FLT0EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM_FLT0EXMIN (FLT0EXMIN)

Extremes detector minimum register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0EXMIN DFSDM_FLT0EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : EXMIN
bits : 8 - 31 (24 bit)


DFSDM_FLT0CNVTIMR (FLT0CNVTIMR)

conversion timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CNVTIMR DFSDM_FLT0CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)


CH0DLYR

channel y delay register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DLYR CH0DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_FLT1CR1 (FLT1CR1)

control register 1
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CR1 DFSDM_FLT1CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM_FLT1CR2 (FLT1CR2)

control register 2
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CR2 DFSDM_FLT1CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM_FLT1ISR (FLT1ISR)

interrupt and status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1ISR DFSDM_FLT1ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM1_ICR (FLT1ICR)

interrupt flag clear register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_ICR DFSDM1_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM_FLT1JCHGR (FLT1CHGR)

injected channel group selection register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1JCHGR DFSDM_FLT1JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM1_FCR (FLT1FCR)

filter control register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_FCR DFSDM1_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)


DFSDM_FLT1JDATAR (FLT1JDATAR)

data register for injected group
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1JDATAR DFSDM_FLT1JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT1RDATAR (FLT1RDATAR)

data register for the regular channel
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1RDATAR DFSDM_FLT1RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT1AWHTR (FLT1AWHTR)

analog watchdog high threshold register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWHTR DFSDM_FLT1AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT1AWLTR (FLT1AWLTR)

analog watchdog low threshold register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWLTR DFSDM_FLT1AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT1AWSR (FLT1AWSR)

analog watchdog status register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWSR DFSDM_FLT1AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT1AWCFR (FLT1AWCFR)

analog watchdog clear flag register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWCFR DFSDM_FLT1AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT1EXMAX (FLT1EXMAX)

Extremes detector maximum register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1EXMAX DFSDM_FLT1EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM_FLT1EXMIN (FLT1EXMIN)

Extremes detector minimum register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1EXMIN DFSDM_FLT1EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : EXMIN
bits : 8 - 31 (24 bit)


DFSDM_FLT1CNVTIMR (FLT1CNVTIMR)

conversion timer register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CNVTIMR DFSDM_FLT1CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)


CH1CFGR1

CH1CFGR1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CFGR1 CH1CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)


DFSDM_FLT2CR1 (FLT2CR1)

control register 1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CR1 DFSDM_FLT2CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM_FLT2CR2 (FLT2CR2)

control register 2
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CR2 DFSDM_FLT2CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM_FLT2ISR (FLT2ISR)

interrupt and status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2ISR DFSDM_FLT2ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM_FLT2ICR (FLT2ICR)

interrupt flag clear register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2ICR DFSDM_FLT2ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM_FLT2JCHGR (FLT2JCHGR)

injected channel group selection register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2JCHGR DFSDM_FLT2JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM_FLT2FCR (FLT2FCR)

filter control register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2FCR DFSDM_FLT2FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)


DFSDM_FLT2JDATAR (FLT2JDATAR)

data register for injected group
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2JDATAR DFSDM_FLT2JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT2RDATAR (FLT2RDATAR)

data register for the regular channel
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2RDATAR DFSDM_FLT2RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT2AWHTR (FLT2AWHTR)

analog watchdog high threshold register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWHTR DFSDM_FLT2AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT2AWLTR (FLT2AWLTR)

analog watchdog low threshold register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWLTR DFSDM_FLT2AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT2AWSR (FLT2AWSR)

analog watchdog status register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWSR DFSDM_FLT2AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT2AWCFR (FLT2AWCFR)

analog watchdog clear flag register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWCFR DFSDM_FLT2AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT2EXMAX (FLT2EXMAX)

Extremes detector maximum register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2EXMAX DFSDM_FLT2EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM_FLT2EXMIN (FLT2EXMIN)

Extremes detector minimum register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2EXMIN DFSDM_FLT2EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : EXMIN
bits : 8 - 31 (24 bit)


DFSDM_FLT2CNVTIMR (FLT2CNVTIMR)

conversion timer register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CNVTIMR DFSDM_FLT2CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)


CH1CFGR2

CH1CFGR2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CFGR2 CH1CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH1AWSCDR

CH1AWSCDR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1AWSCDR CH1AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_FLT3CR1 (FLT3CR1)

control register 1
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CR1 DFSDM_FLT3CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM_FLT3CR2 (FLT3CR2)

control register 2
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CR2 DFSDM_FLT3CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM_FLT3ISR (FLT3ISR)

interrupt and status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3ISR DFSDM_FLT3ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM_FLT3ICR (FLT3ICR)

interrupt flag clear register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3ICR DFSDM_FLT3ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM_FLT3JCHGR (FLT3JCHGR)

injected channel group selection register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3JCHGR DFSDM_FLT3JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM_FLT3FCR (FLT3FCR)

filter control register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3FCR DFSDM_FLT3FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)


DFSDM_FLT3JDATAR (FLT3JDATAR)

data register for injected group
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3JDATAR DFSDM_FLT3JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT3RDATAR (FLT3RDATAR)

data register for the regular channel
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3RDATAR DFSDM_FLT3RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM_FLT3AWHTR (FLT3AWHTR)

analog watchdog high threshold register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWHTR DFSDM_FLT3AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT3AWLTR (FLT3AWLTR)

analog watchdog low threshold register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWLTR DFSDM_FLT3AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM_FLT3AWSR (FLT3AWSR)

analog watchdog status register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWSR DFSDM_FLT3AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT3AWCFR (FLT3AWCFR)

analog watchdog clear flag register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWCFR DFSDM_FLT3AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM_FLT3EXMAX (FLT3EXMAX)

Extremes detector maximum register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3EXMAX DFSDM_FLT3EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM_FLT3EXMIN (FLT3EXMIN)

Extremes detector minimum register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3EXMIN DFSDM_FLT3EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : EXMIN
bits : 8 - 31 (24 bit)


DFSDM_FLT3CNVTIMR (FLT3CNVTIMR)

conversion timer register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CNVTIMR DFSDM_FLT3CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)


CH1WDATR

CH1WDATR
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1WDATR CH1WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH1DATINR

CH1DATINR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1DATINR CH1DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


CH1DLYR

channel y delay register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1DLYR CH1DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


CH0CFGR2

channel configuration y register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CFGR2 CH0CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH2CFGR1

CH2CFGR1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CFGR1 CH2CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)


CH2CFGR2

CH2CFGR2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CFGR2 CH2CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH2AWSCDR

CH2AWSCDR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2AWSCDR CH2AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


CH2WDATR

CH2WDATR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2WDATR CH2WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH2DATINR

CH2DATINR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2DATINR CH2DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


CH2DLYR

channel y delay register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2DLYR CH2DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


CH3CFGR1

CH3CFGR1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CFGR1 CH3CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)


CH3CFGR2

CH3CFGR2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CFGR2 CH3CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH3AWSCDR

CH3AWSCDR
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3AWSCDR CH3AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


CH3WDATR

CH3WDATR
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3WDATR CH3WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH3DATINR

CH3DATINR
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3DATINR CH3DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


CH3DLYR

channel y delay register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3DLYR CH3DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


CH0AWSCDR

analog watchdog and short-circuit detector register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0AWSCDR CH0AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


CH4CFGR1

CH4CFGR1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CFGR1 CH4CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)


CH4CFGR2

CH4CFGR2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CFGR2 CH4CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH4AWSCDR

CH4AWSCDR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4AWSCDR CH4AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


CH4WDATR

CH4WDATR
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4WDATR CH4WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH4DATINR

CH4DATINR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4DATINR CH4DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


CH4DLYR

channel y delay register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4DLYR CH4DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


CH5CFGR1

CH5CFGR1
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CFGR1 CH5CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)


CH5CFGR2

CH5CFGR2
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CFGR2 CH5CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH5AWSCDR

CH5AWSCDR
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5AWSCDR CH5AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


CH5WDATR

CH5WDATR
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5WDATR CH5WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH5DATINR

CH5DATINR
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5DATINR CH5DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


CH5DLYR

channel y delay register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5DLYR CH5DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


CH0WDATR

channel watchdog filter data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0WDATR CH0WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH6CFGR1

CH6CFGR1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CFGR1 CH6CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)


CH6CFGR2

CH6CFGR2
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CFGR2 CH6CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH6AWSCDR

CH6AWSCDR
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6AWSCDR CH6AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


CH6WDATR

CH6WDATR
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6WDATR CH6WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH6DATINR

CH6DATINR
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6DATINR CH6DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


CH6DLYR

channel y delay register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6DLYR CH6DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


CH7CFGR1

CH7CFGR1
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CFGR1 CH7CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)


CH7CFGR2

CH7CFGR2
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CFGR2 CH7CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


CH7AWSCDR

CH7AWSCDR
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7AWSCDR CH7AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


CH7WDATR

CH7WDATR
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7WDATR CH7WDATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


CH7DATINR

CH7DATINR
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7DATINR CH7DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


CH7DLYR

channel y delay register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7DLYR CH7DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)



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