RTC_TR (TR)

RTC_PRER (PRER)

RTC_WUTR (WUTR)

RTC_CR (CR)

RTC_WPR (WPR)

RTC_CALR (CALR)

RTC_SHIFTR (SHIFTR)

RTC_TSTR (TSTR)

RTC_TSDR (TSDR)

RTC_TSSSR (TSSSR)

RTC_DR (DR)

RTC_ALRMAR (ALRMAR)

RTC_ALRMASSR (ALRMASSR)

RTC_ALRMBR (ALRMBR)

RTC_ALRMBSSR (ALRMBSSR)

RTC_SR (SR)

RTC_MISR (MISR)

RTC_SCR (SCR)

RTC_CFGR (CFGR)

RTC_SSR (SSR)

RTC_ICSR (ICSR)

SU : Second units in BCD format
bits : 0 - 3 (4 bit)
access : read-write

ST : Second tens in BCD format
bits : 4 - 6 (3 bit)
access : read-write

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)
access : read-write

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)
access : read-write

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)
access : read-write

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)
access : read-write

PM : AM/PM notation
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PREDIV_S : Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
bits : 0 - 14 (15 bit)
access : read-write

PREDIV_A : Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
bits : 16 - 22 (7 bit)
access : read-write

WUT : Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.
bits : 0 - 15 (16 bit)
access : read-write

WUCKSEL : ck_wut wakeup clock selection 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TSEDGE : Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFCKON : RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: PREDIV_S must be 0x00FF.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BYPSHAD : Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FMT : Hour format
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALRAE : Alarm A enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALRBE : Alarm B enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WUTE : Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TSE : timestamp enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALRAIE : Alarm A interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALRBIE : Alarm B interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WUTIE : Wakeup timer interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TSIE : Timestamp interrupt enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADD1H : Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
bits : 16 - 16 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SUB1H : Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
bits : 17 - 17 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

BKP : Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
bits : 18 - 18 (1 bit)
access : read-write

COSEL : Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POL : Output polarity This bit is used to configure the polarity of TAMPALRM output.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSEL : Output selection These bits are used to select the flag to be routed to TAMPALRM output.
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COE : Calibration output enable This bit enables the CALIB output
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ITSE : timestamp on internal event enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMPTS : Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMPOE : Tamper detection output enable on TAMPALRM
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMPALRM_PU : TAMPALRM pull-up enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMPALRM_TYPE : TAMPALRM output type
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OUT2EN : RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL ≠ 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.
bits : 31 - 31 (1 bit)
access : read-write

KEY : Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection.
bits : 0 - 7 (8 bit)
access : write-only

CALM : Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See .
bits : 0 - 8 (9 bit)
access : read-write

CALW16 : Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration.
bits : 13 - 13 (1 bit)
access : read-write

CALW8 : Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration.
bits : 14 - 14 (1 bit)
access : read-write

CALP : Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) - CALM. Refer to .
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUBFS : Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.
bits : 0 - 14 (15 bit)
access : write-only

ADD1S : Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
bits : 31 - 31 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SU : Second units in BCD format.
bits : 0 - 3 (4 bit)
access : read-only

ST : Second tens in BCD format.
bits : 4 - 6 (3 bit)
access : read-only

MNU : Minute units in BCD format.
bits : 8 - 11 (4 bit)
access : read-only

MNT : Minute tens in BCD format.
bits : 12 - 14 (3 bit)
access : read-only

HU : Hour units in BCD format.
bits : 16 - 19 (4 bit)
access : read-only

HT : Hour tens in BCD format.
bits : 20 - 21 (2 bit)
access : read-only

PM : AM/PM notation
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DU : Date units in BCD format
bits : 0 - 3 (4 bit)
access : read-only

DT : Date tens in BCD format
bits : 4 - 5 (2 bit)
access : read-only

MU : Month units in BCD format
bits : 8 - 11 (4 bit)
access : read-only

MT : Month tens in BCD format
bits : 12 - 12 (1 bit)
access : read-only

WDU : Week day units
bits : 13 - 15 (3 bit)
access : read-only

SS : Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred.
bits : 0 - 15 (16 bit)
access : read-only

DU : Date units in BCD format
bits : 0 - 3 (4 bit)
access : read-write

DT : Date tens in BCD format
bits : 4 - 5 (2 bit)
access : read-write

MU : Month units in BCD format
bits : 8 - 11 (4 bit)
access : read-write

MT : Month tens in BCD format
bits : 12 - 12 (1 bit)
access : read-write

WDU : Week day units ...
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

YU : Year units in BCD format
bits : 16 - 19 (4 bit)
access : read-write

YT : Year tens in BCD format
bits : 20 - 23 (4 bit)
access : read-write

SU : Second units in BCD format.
bits : 0 - 3 (4 bit)
access : read-write

ST : Second tens in BCD format.
bits : 4 - 6 (3 bit)
access : read-write

MSK1 : Alarm A seconds mask
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)
access : read-write

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)
access : read-write

MSK2 : Alarm A minutes mask
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)
access : read-write

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)
access : read-write

PM : AM/PM notation
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSK3 : Alarm A hours mask
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DU : Date units or day in BCD format
bits : 24 - 27 (4 bit)
access : read-write

DT : Date tens in BCD format
bits : 28 - 29 (2 bit)
access : read-write

WDSEL : Week day selection
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSK4 : Alarm A date mask
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS : Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
bits : 0 - 14 (15 bit)
access : read-write

MASKSS : Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SU : Second units in BCD format
bits : 0 - 3 (4 bit)
access : read-write

ST : Second tens in BCD format
bits : 4 - 6 (3 bit)
access : read-write

MSK1 : Alarm B seconds mask
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)
access : read-write

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)
access : read-write

MSK2 : Alarm B minutes mask
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)
access : read-write

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)
access : read-write

PM : AM/PM notation
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSK3 : Alarm B hours mask
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DU : Date units or day in BCD format
bits : 24 - 27 (4 bit)
access : read-write

DT : Date tens in BCD format
bits : 28 - 29 (2 bit)
access : read-write

WDSEL : Week day selection
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSK4 : Alarm B date mask
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS : Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
bits : 0 - 14 (15 bit)
access : read-write

MASKSS : Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALRAF : Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR).
bits : 0 - 0 (1 bit)
access : read-only

ALRBF : Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR).
bits : 1 - 1 (1 bit)
access : read-only

WUTF : Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
bits : 2 - 2 (1 bit)
access : read-only

TSF : Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
bits : 3 - 3 (1 bit)
access : read-only

TSOVF : Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
bits : 4 - 4 (1 bit)
access : read-only

ITSF : Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs.
bits : 5 - 5 (1 bit)
access : read-only

ALRAMF : Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs.
bits : 0 - 0 (1 bit)
access : read-only

ALRBMF : Alarm B masked flag This flag is set by hardware when the alarm B interrupt occurs.
bits : 1 - 1 (1 bit)
access : read-only

WUTMF : Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
bits : 2 - 2 (1 bit)
access : read-only

TSMF : Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
bits : 3 - 3 (1 bit)
access : read-only

TSOVMF : Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
bits : 4 - 4 (1 bit)
access : read-only

ITSMF : Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.
bits : 5 - 5 (1 bit)
access : read-only

CALRAF : Clear alarm A flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
bits : 0 - 0 (1 bit)
access : write-only

CALRBF : Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
bits : 1 - 1 (1 bit)
access : write-only

CWUTF : Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register.
bits : 2 - 2 (1 bit)
access : write-only

CTSF : Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.
bits : 3 - 3 (1 bit)
access : write-only

CTSOVF : Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
bits : 4 - 4 (1 bit)
access : write-only

CITSF : Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register.
bits : 5 - 5 (1 bit)
access : write-only

OUT2_RMP : RTC_OUT2 mapping
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS : Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.
bits : 0 - 15 (16 bit)
access : read-only

ALRAWF : Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ALRBWF : Alarm B write flag This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WUTWF : Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SHPF : Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INITS : Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RSF : Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INITF : Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INIT : Initialization mode
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RECALPF : Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .
bits : 16 - 16 (1 bit)
access : read-only