Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4BC byte (0x0)
mem_usage : registers
protection :
DFSDM channel 0 configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
DFSDM channel 0 data input register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
DFSDM channel 1 configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
DFSDM channel 1 configuration register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 1 analog watchdog and short-circuit detector register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
DFSDM channel 1 watchdog filter data register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 1 data input register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
DFSDM channel 0 configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 2 configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
DFSDM channel 2 configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 2 analog watchdog and short-circuit detector register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.
0x1 : B_0x1
DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.
End of enumeration elements list.
JSWSTART : Start a conversion of the injected group of channels This bit is always read as '0â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect.
0x1 : B_0x1
Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1.
End of enumeration elements list.
JSYNC : Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch an injected conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
End of enumeration elements list.
JSCAN : Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.
0x1 : B_0x1
The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.
End of enumeration elements list.
JDMAEN : DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read injected data
0x1 : B_0x1
The DMA channel is enabled to read injected data
End of enumeration elements list.
JEXTSEL : Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
bits : 8 - 12 (5 bit)
access : read-write
JEXTEN : Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger detection is disabled
0x1 : B_0x1
Each rising edge on the selected trigger makes a request to launch an injected conversion
0x2 : B_0x2
Each falling edge on the selected trigger makes a request to launch an injected conversion
0x3 : B_0x3
Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
End of enumeration elements list.
RSWSTART : Software start of a conversion on the regular channel This bit is always read as '0â.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1.
End of enumeration elements list.
RCONT : Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The regular channel is converted just once for each conversion request
0x1 : B_0x1
The regular channel is converted repeatedly after each conversion request
End of enumeration elements list.
RSYNC : Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Do not launch a regular conversion synchronously with DFSDM_FLT0
0x1 : B_0x1
Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
End of enumeration elements list.
RDMAEN : DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The DMA channel is not enabled to read regular data
0x1 : B_0x1
The DMA channel is enabled to read regular data
End of enumeration elements list.
RCH : Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel 0 is selected as the regular channel
0x1 : B_0x1
Channel 1 is selected as the regular channel
End of enumeration elements list.
FAST : Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Fast conversion mode disabled
0x1 : B_0x1
Fast conversion mode enabled
End of enumeration elements list.
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
0x1 : B_0x1
Analog watchdog on channel transceivers value (after watchdog filter)
End of enumeration elements list.
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected end of conversion interrupt is disabled
0x1 : B_0x1
Injected end of conversion interrupt is enabled
End of enumeration elements list.
REOCIE : Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular end of conversion interrupt is disabled
0x1 : B_0x1
Regular end of conversion interrupt is enabled
End of enumeration elements list.
JOVRIE : Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Injected data overrun interrupt is disabled
0x1 : B_0x1
Injected data overrun interrupt is enabled
End of enumeration elements list.
ROVRIE : Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Regular data overrun interrupt is disabled
0x1 : B_0x1
Regular data overrun interrupt is enabled
End of enumeration elements list.
AWDIE : Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt is disabled
0x1 : B_0x1
Analog watchdog interrupt is enabled
End of enumeration elements list.
SCDIE : Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
short-circuit detector interrupt is disabled
0x1 : B_0x1
short-circuit detector interrupt is enabled
End of enumeration elements list.
CKABIE : Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection of channel input clock absence interrupt is disabled
0x1 : B_0x1
Detection of channel input clock absence interrupt is enabled
End of enumeration elements list.
EXCH : Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
bits : 8 - 15 (8 bit)
access : read-write
AWDCH : Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
bits : 16 - 23 (8 bit)
access : read-write
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion has completed
0x1 : B_0x1
An injected conversion has completed and its data may be read
End of enumeration elements list.
REOCF : End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion has completed
0x1 : B_0x1
A regular conversion has completed and its data may be read
End of enumeration elements list.
JOVRF : Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No injected conversion overrun has occurred
0x1 : B_0x1
An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns
End of enumeration elements list.
ROVRF : Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No regular conversion overrun has occurred
0x1 : B_0x1
A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns
End of enumeration elements list.
AWDF : Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register).
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Analog watchdog event occurred
0x1 : B_0x1
The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
End of enumeration elements list.
JCIP : Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the injected channel group (neither by software nor by trigger) has been issued
0x1 : B_0x1
The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection
End of enumeration elements list.
RCIP : Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No request to convert the regular channel has been issued
0x1 : B_0x1
The conversion of the regular channel is in progress or a request for a regular conversion is pending
End of enumeration elements list.
CKABF : Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-only
SCDF : short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-only
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Writing '0â has no effect
0x1 : B_0x1
Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register
End of enumeration elements list.
CLRCKABF : Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 16 - 23 (8 bit)
access : read-write
CLRSCDF : Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
bits : 24 - 31 (8 bit)
access : read-write
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
bits : 0 - 7 (8 bit)
access : read-write
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
bits : 0 - 7 (8 bit)
access : read-write
FOSR : Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
bits : 16 - 25 (10 bit)
access : read-write
FORD : Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
JDATA : Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
bits : 0 - 2 (3 bit)
access : read-only
RPEND : Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
bits : 4 - 4 (1 bit)
access : read-only
RDATA : Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWHT : Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
bits : 0 - 3 (4 bit)
access : read-write
AWLT : Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 0 - 7 (8 bit)
access : read-only
AWHTF : Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
bits : 8 - 15 (8 bit)
access : read-only
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0â has no effect CLRAWLTF[y]=1: Writing '1â to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
bits : 0 - 7 (8 bit)
access : read-write
CLRAWHTF : Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0â has no effect CLRAWHTF[y]=1: Writing '1â to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
bits : 8 - 15 (8 bit)
access : read-write
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMAX : Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-only
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
bits : 8 - 31 (24 bit)
access : read-write
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
bits : 4 - 31 (28 bit)
access : read-only
DFSDM channel 2 watchdog filter data register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 2 data input register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
DFSDM channel 3 configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
DFSDM channel 3 configuration register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 3 analog watchdog and short-circuit detector register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
DFSDM channel 3 watchdog filter data register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 3 data input register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
DFSDM channel 0 analog watchdog and short-circuit detector register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
DFSDM channel 4 configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
DFSDM channel 4 configuration register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 4 analog watchdog and short-circuit detector register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
DFSDM channel 4 watchdog filter data register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 4 data input register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
DFSDM channel 5 configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
DFSDM channel 5 configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 5 analog watchdog and short-circuit detector register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
DFSDM channel 5 watchdog filter data register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 5 data input register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
DFSDM channel 0 watchdog filter data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 6 configuration register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
DFSDM channel 6 configuration register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 6 analog watchdog and short-circuit detector register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
DFSDM channel 6 watchdog filter data register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 6 data input register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
DFSDM channel 7 configuration register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI with rising edge to strobe data
0x1 : B_0x1
SPI with falling edge to strobe data
0x2 : B_0x2
Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
0x3 : B_0x3
Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
End of enumeration elements list.
SPICKSEL : SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external 룉 modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock coming from external CKINy input - sampling point according SITP[1:0]
0x1 : B_0x1
clock coming from internal CKOUT output - sampling point according SITP[1:0]
End of enumeration elements list.
SCDEN : Short-circuit detector enable on channel y
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input channel y will not be guarded by the short-circuit detector
0x1 : B_0x1
Input channel y will be continuously guarded by the short-circuit detector
End of enumeration elements list.
CKABEN : Clock absence detector enable on channel y
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock absence detector disabled on channel y
0x1 : B_0x1
Clock absence detector enabled on channel y
End of enumeration elements list.
CHEN : Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel y disabled
0x1 : B_0x1
Channel y enabled
End of enumeration elements list.
CHINSEL : Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel inputs are taken from pins of the same channel y.
0x1 : B_0x1
Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
End of enumeration elements list.
DATMPX : Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.
0x1 : B_0x1
Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.
End of enumeration elements list.
DATPACK : Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
0x1 : B_0x1
Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
End of enumeration elements list.
CKOUTDIV : Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Output clock generation is disabled (CKOUT signal is set to low state)
End of enumeration elements list.
CKOUTSRC : Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Source for output clock is from system clock
0x1 : B_0x1
Source for output clock is from audio clock
End of enumeration elements list.
DFSDMEN : Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DFSDM interface disabled
0x1 : B_0x1
DFSDM interface enabled
End of enumeration elements list.
DFSDM channel 7 configuration register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
bits : 3 - 7 (5 bit)
access : read-write
OFFSET : 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
bits : 8 - 31 (24 bit)
access : read-write
DFSDM channel 7 analog watchdog and short-circuit detector register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
bits : 0 - 7 (8 bit)
access : read-write
BKSCD : Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
bits : 12 - 15 (4 bit)
access : read-write
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
bits : 16 - 20 (5 bit)
access : read-write
AWFORD : Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FastSinc filter type
0x1 : B_0x1
Sinc1 filter type
End of enumeration elements list.
DFSDM channel 7 watchdog filter data register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
bits : 0 - 15 (16 bit)
access : read-only
DFSDM channel 7 data input register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
bits : 0 - 15 (16 bit)
access : read-write
INDAT1 : Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
bits : 16 - 31 (16 bit)
access : read-write
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
bits : 0 - 5 (6 bit)
access : read-write
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