Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
DMA interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF1 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 0 - 0 (1 bit)
TCIF1 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 1 - 1 (1 bit)
HTIF1 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 2 - 2 (1 bit)
TEIF1 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 3 - 3 (1 bit)
GIF2 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 4 - 4 (1 bit)
TCIF2 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 5 - 5 (1 bit)
HTIF2 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 6 - 6 (1 bit)
TEIF2 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 7 - 7 (1 bit)
GIF3 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 8 - 8 (1 bit)
TCIF3 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 9 - 9 (1 bit)
HTIF3 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 10 - 10 (1 bit)
TEIF3 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 11 - 11 (1 bit)
GIF4 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 12 - 12 (1 bit)
TCIF4 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 13 - 13 (1 bit)
HTIF4 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 14 - 14 (1 bit)
TEIF4 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 15 - 15 (1 bit)
GIF5 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 16 - 16 (1 bit)
TCIF5 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 17 - 17 (1 bit)
HTIF5 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 18 - 18 (1 bit)
TEIF5 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 19 - 19 (1 bit)
GIF6 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 20 - 20 (1 bit)
TCIF6 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 21 - 21 (1 bit)
HTIF6 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 22 - 22 (1 bit)
TEIF6 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 23 - 23 (1 bit)
GIF7 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 24 - 24 (1 bit)
TCIF7 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 25 - 25 (1 bit)
HTIF7 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 26 - 26 (1 bit)
TEIF7 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 27 - 27 (1 bit)
GIF8 : Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 28 - 28 (1 bit)
TCIF8 : Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 29 - 29 (1 bit)
HTIF8 : Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 30 - 30 (1 bit)
TEIF8 : Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
bits : 31 - 31 (1 bit)
This register must not be written when the channel is enabled.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
This register must not be written when the channel is enabled.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
BDMA_CMAR1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
This register must not be written when the channel is enabled.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
DMA interrupt flag clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CGIF1 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
CTCIF1 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
CHTIF1 : Channel x half transfer clear This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
CTEIF1 : Channel x transfer error clear This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
CGIF2 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CTCIF2 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
CHTIF2 : Channel x half transfer clear This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
CTEIF2 : Channel x transfer error clear This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
CGIF3 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 8 - 8 (1 bit)
CTCIF3 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 9 - 9 (1 bit)
CHTIF3 : Channel x half transfer clear This bit is set and cleared by software.
bits : 10 - 10 (1 bit)
CTEIF3 : Channel x transfer error clear This bit is set and cleared by software.
bits : 11 - 11 (1 bit)
CGIF4 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 12 - 12 (1 bit)
CTCIF4 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 13 - 13 (1 bit)
CHTIF4 : Channel x half transfer clear This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
CTEIF4 : Channel x transfer error clear This bit is set and cleared by software.
bits : 15 - 15 (1 bit)
CGIF5 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 16 - 16 (1 bit)
CTCIF5 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 17 - 17 (1 bit)
CHTIF5 : Channel x half transfer clear This bit is set and cleared by software.
bits : 18 - 18 (1 bit)
CTEIF5 : Channel x transfer error clear This bit is set and cleared by software.
bits : 19 - 19 (1 bit)
CGIF6 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 20 - 20 (1 bit)
CTCIF6 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 21 - 21 (1 bit)
CHTIF6 : Channel x half transfer clear This bit is set and cleared by software.
bits : 22 - 22 (1 bit)
CTEIF6 : Channel x transfer error clear This bit is set and cleared by software.
bits : 23 - 23 (1 bit)
CGIF7 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 24 - 24 (1 bit)
CTCIF7 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 25 - 25 (1 bit)
CHTIF7 : Channel x half transfer clear This bit is set and cleared by software.
bits : 26 - 26 (1 bit)
CTEIF7 : Channel x transfer error clear This bit is set and cleared by software.
bits : 27 - 27 (1 bit)
CGIF8 : Channel x global interrupt clear This bit is set and cleared by software.
bits : 28 - 28 (1 bit)
CTCIF8 : Channel x transfer complete clear This bit is set and cleared by software.
bits : 29 - 29 (1 bit)
CHTIF8 : Channel x half transfer clear This bit is set and cleared by software.
bits : 30 - 30 (1 bit)
CTEIF8 : Channel x transfer error clear This bit is set and cleared by software.
bits : 31 - 31 (1 bit)
BDMA_CM1AR2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
This register must not be written when the channel is enabled.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
BDMA_CMAR3
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
This register must not be written when the channel is enabled.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
BDMA_CM1AR4
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
This register must not be written when the channel is enabled.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
This register must not be written when the channel is enabled.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x configuration register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable This bit is set and cleared by software.
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable This bit is set and cleared by software.
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable This bit is set and cleared by software.
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable This bit is set and cleared by software.
bits : 3 - 3 (1 bit)
DIR : Data transfer direction This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
CIRC : Circular mode This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
MINC : Memory increment mode This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size These bits are set and cleared by software.
bits : 8 - 9 (2 bit)
MSIZE : Memory size These bits are set and cleared by software.
bits : 10 - 11 (2 bit)
PL : Channel priority level These bits are set and cleared by software.
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
DMA channel x number of data register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
This register must not be written when the channel is enabled.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
bits : 0 - 31 (32 bit)
This register must not be written when the channel is enabled.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA channel x number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.
bits : 0 - 15 (16 bit)
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