RCC_CR (CR)

RCC_CFGR (CFGR)

RCC_RSR (RSR)

RCC_AHB3ENR (AHB3ENR)

RCC_AHB1ENR (AHB1ENR)

RCC_AHB2ENR (AHB2ENR)

RCC_AHB4ENR (AHB4ENR)

RCC_APB3ENR (APB3ENR)

RCC_APB1LENR (APB1LENR)

RCC_APB1HENR (APB1HENR)

RCC_APB2ENR (APB2ENR)

RCC_APB4ENR (APB4ENR)

RCC_AHB3LPENR (AHB3LPENR)

RCC_AHB1LPENR (AHB1LPENR)

RCC_AHB2LPENR (AHB2LPENR)

RCC_AHB4LPENR (AHB4LPENR)

RCC_APB3LPENR (APB3LPENR)

RCC_APB1LLPENR (APB1LLPENR)

RCC_APB1HLPENR (APB1HLPENR)

RCC_APB2LPENR (APB2LPENR)

RCC_APB4LPENR (APB4LPENR)

RCC_CDCFGR1 (CDCFGR1)

RCC_CDCFGR2 (CDCFGR2)

RCC_SRDCFGR (SRDCFGR)

RCC_PLLCKSELR (PLLCKSELR)

RCC_PLLCFGR (PLLCFGR)

RCC_PLL1DIVR (PLL1DIVR)

RCC_PLL1FRACR (PLL1FRACR)

RCC_PLL2DIVR (PLL2DIVR)

RCC_PLL2FRACR (PLL2FRACR)

RCC_HSICFGR (HSICFGR)

RCC_PLL3DIVR (PLL3DIVR)

RCC_PLL3FRACR (PLL3FRACR)

RCC_CDCCIPR (CDCCIPR)

RCC_CDCCIP1R (CDCCIP1R)

RCC_CDCCIP2R (CDCCIP2R)

RCC_SRDCCIPR (SRDCCIPR)

RCC_CIER (CIER)

RCC_CIFR (CIFR)

RCC_CICR (CICR)

RCC_BDCR (BDCR)

RCC_CSR (CSR)

RCC_AHB3RSTR (AHB3RSTR)

RCC_CRRCR (CRRCR)

RCC_AHB1RSTR (AHB1RSTR)

RCC_AHB2RSTR (AHB2RSTR)

RCC_AHB4RSTR (AHB4RSTR)

RCC_APB3RSTR (APB3RSTR)

RCC_APB1LRSTR (APB1LRSTR)

RCC_APB1HRSTR (APB1HRSTR)

RCC_APB2RSTR (APB2RSTR)

RCC_APB4RSTR (APB4RSTR)

RCC_SRDAMR (SRDAMR)

RCC_CKGAENR (CKGAENR)

RCC_CSICFGR (CSICFGR)

HSION : HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSIKERON : HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSIRDY : HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HSIDIV : HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored.
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSIDIVF : HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed)
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CSION : CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CSIRDY : CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CSIKERON : CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSI48ON : HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSI48RDY : HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CPUCKRDY : CPU related clocks ready flag Set by hardware to indicate that the CPU related clocks (CPU, APB3, AXI bus matrix and related memories) are available.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CDCKRDY : CPU domain clocks ready flag Set by hardware to indicate that the following CPU domain clocks are available: APB1, APB2, AHB bus matrix.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HSEON : HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSERDY : HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HSEBYP : HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSECSSON : HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSEEXT : external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL1ON : PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL1RDY : PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLL2ON : PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL2RDY : PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked.
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLL3ON : PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL3RDY : PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked.
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SW : system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck and traceclk). Set by hardware in order to: force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWS : system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved
bits : 3 - 5 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STOPWUCK : system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOPKERWUCK : kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See for details.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCPRE : HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ...
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIMPRE : timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. Refer to for more details.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCO1PRE : MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ...
bits : 18 - 21 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCO1SEL : Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCO2PRE : MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ...
bits : 25 - 28 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCO2SEL : microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RMVF : remove reset flag Set and reset by software to reset the value of the reset flags.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDRSTF : CPU domain power-switch reset flag Reset by software by writing the RMVF bit. Set by hardware when a the CPU domain exits from DStop or after of power-on reset. Set also when the CPU domain exists DStop2 but only when a pad reset has occurred during DStop2 (PINRST bit also set by hardware)
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BORRSTF : BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst).
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PINRSTF : pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs.
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PORRSTF : POR/PDR reset flag Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SFTRSTF : system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

IWDGRSTF : independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs.
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WWDGRSTF : window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LPWRRSTF : reset due to illegal CD DStop or CD DStop2 or CPU CStop flag Reset by software by writing the RMVF bit. Set by hardware when the CPU domain goes erroneously in DStop or DStop2, or when the CPU goes erroneously in CStop.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MDMAEN : MDMA peripheral clock enable Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA2DEN : DMA2D peripheral clock enable Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

JPGDECEN : JPGDEC peripheral clock enable Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FMCEN : FMC peripheral clocks enable Set and reset by software. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCTOSPI1EN : OCTOSPI1 and OCTOSPI1 delay clock enable Set and reset by software.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDMMC1EN : SDMMC1 and SDMMC1 delay clock enable Set and reset by software.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCTOSPI2EN : OCTOSPI2 clock enable Set and reset by software.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCTOSPIMEN : OCTOSPIM clock enable Set and reset by software.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OTFD1EN : OTFD1 clock enable Set and reset by software.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OTFD2EN : OTFD2 clock enable Set and reset by software.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GFXMMUEN : GFXMMU clock enable Set and reset by software.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA1EN : DMA1 clock enable Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA2EN : DMA2 clock enable Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC12EN : ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCEN : CRC peripheral clock enable Set and reset by software.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USB1OTGEN : USB1OTG peripheral clocks enable Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USB1ULPIEN : USB_PHY1 clocks enable Set and reset by software.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DCMI_PSSIEN : digital camera interface peripheral clock enable (DCMI or PSSI depending which IP is active) Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSEMEN : HSEM peripheral clock enable Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRYPTEN : CRYPT peripheral clock enable Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HASHEN : HASH peripheral clock enable Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RNGEN : RNG peripheral clocks enable Set and reset by software. The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDMMC2EN : SDMMC2 and SDMMC2 delay clock enable Set and reset by software.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BDMA1EN : DMA clock enable (DFSDM dedicated DMA) Set and reset by software.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AHBSRAM1EN : AHBSRAM1 block enable Set and reset by software. When set, this bit indicates that the SRAM1 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AHBSRAM2EN : AHBSRAM2 block enable Set and reset by software. When set, this bit indicates that the SRAM2 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOAEN : GPIOA peripheral clock enable Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOBEN : GPIOB peripheral clock enable Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOCEN : GPIOC peripheral clock enable Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIODEN : GPIOD peripheral clock enable Set and reset by software.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOEEN : GPIOE peripheral clock enable Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOFEN : GPIOF peripheral clock enable Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOGEN : GPIOG peripheral clock enable Set and reset by software.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOHEN : GPIOH peripheral clock enable Set and reset by software.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOIEN : GPIOI peripheral clock enable Set and reset by software.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOJEN : GPIOJ peripheral clock enable Set and reset by software.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOKEN : GPIOK peripheral clock enable Set and reset by software.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BDMA2EN : SmartRun domain DMA and DMAMUX clock enable Set and reset by software.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKPRAMEN : Backup RAM clock enable Set and reset by software.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRDSRAMEN : SmartRun domain SRAM clock enable Set and reset by software.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LTDCEN : LTDC clock enable Provides the clock (ltdc_pclk, ltdc_aclk, ltdc_ker_ck) to the LTDC block. Set and reset by software.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WWDGEN : WWDG clock enable Set by software, and reset by hardware when a system reset occurs. Note that in order to work properly, before enabling the WWDG, the bit WW1RSC must be set to 1.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM2EN : TIM2 peripheral clock enable Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM3EN : TIM3 peripheral clock enable Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM4EN : TIM4 peripheral clock enable Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM5EN : TIM5 peripheral clock enable Set and reset by software.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM6EN : TIM6 peripheral clock enable Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM7EN : TIM7 peripheral clock enable Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM12EN : TIM12 peripheral clock enable Set and reset by software.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM13EN : TIM13 peripheral clock enable Set and reset by software.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM14EN : TIM14 peripheral clock enable Set and reset by software.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPTIM1EN : LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2EN : SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI3EN : SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPDIFRXEN : SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART2EN : USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART3EN : USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART4EN : UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART5EN : UART5 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART5 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1EN : I2C1 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C1 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C2EN : I2C2 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C2 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C3EN : I2C3 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C3 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CECEN : HDMI-CEC peripheral clock enable Set and reset by software. The peripheral clocks of the HDMI-CEC are the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAC1EN : DAC1 (containing two converters) peripheral clock enable Set and reset by software.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART7EN : UART7 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART7 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART8EN : UART8 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART8 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRSEN : clock recovery system peripheral clock enable Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWPMIEN : SWPMI peripheral clocks enable Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPAMPEN : OPAMP peripheral clock enable Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MDIOSEN : MDIOS peripheral clock enable Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDCANEN : FDCAN peripheral clocks enable Set and reset by software. The peripheral clocks of the FDCAN are the kernel clock selected by FDCANSEL and provided to fdcan_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM1EN : TIM1 peripheral clock enable Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM8EN : TIM8 peripheral clock enable Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART1EN : USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART6EN : USART6 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART9EN : UART9 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART10EN : USART10 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1EN : SPI1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI4EN : SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM15EN : TIM15 peripheral clock enable Set and reset by software.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM16EN : TIM16 peripheral clock enable Set and reset by software.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM17EN : TIM17 peripheral clock enable Set and reset by software.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI5EN : SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAI1EN : SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAI2EN : SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFSDM1EN : DFSDM1 peripheral clocks enable Set and reset by software. DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively,
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCFGEN : SYSCFG peripheral clock enable Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPUART1EN : LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI6EN : SPI6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to spi_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C4EN : I2C4 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPTIM2EN : LPTIM2 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPTIM3EN : LPTIM3 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAC2EN : DAC2 (containing one converter) peripheral clock enable Set and reset by software.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMP12EN : COMP1 and 2 peripheral clock enable Set and reset by software.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VREFEN : VREF peripheral clock enable Set and reset by software.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCAPBEN : RTC APB clock enable Set and reset by software.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTSEN : Digital temperature sensor peripheral clock enable Set and reset by software.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFSDM2EN : DFSDM2peripheral clock enable Set and reset by software.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MDMALPEN : MDMA clock enable during CSleep mode Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA2DLPEN : DMA2D clock enable during CSleep mode Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

JPGDECLPEN : JPGDEC clock enable during CSleep mode Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLITFLPEN : FLITF clock enable during CSleep mode Set and reset by software.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FMCLPEN : FMC peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCTOSPI1LPEN : OCTOSPI1 and OCTOSPI1 delay clock enable during CSleep mode Set and reset by software.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDMMC1LPEN : SDMMC1 and SDMMC1 delay clock enable during CSleep mode Set and reset by software.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCTOSPI2LPEN : OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode Set and reset by software.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCTOSPIMLPEN : OCTOSPIM block clock enable during CSleep mode Set and reset by software.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OTFD1LPEN : OTFD1 block clock enable during CSleep mode Set and reset by software.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OTFD2LPEN : OTFD2 block clock enable during CSleep mode Set and reset by software.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GFXMMULPEN : GFXMMU block clock enable during CSleep mode Set and reset by software.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AXISRAM2LPEN : AXISRAM2 block clock enable during CSleep mode Set and reset by software.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AXISRAM3LPEN : AXISRAM3 block clock enable during CSleep mode Set and reset by software.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCM1LPEN : DTCM1 block clock enable during CSleep mode Set and reset by software.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCM2LPEN : DTCM2 block clock enable during CSleep mode Set and reset by software.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ITCMLPEN : ITCM block clock enable during CSleep mode Set and reset by software.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AXISRAM1LPEN : AXISRAM1 block clock enable during CSleep mode Set and reset by software.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA1LPEN : DMA1 clock enable during CSleep mode Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA2LPEN : DMA2 clock enable during CSleep mode Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC12LPEN : ADC1 and 2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCLPEN : CRC peripheral clock enable during CSleep mode Set and reset by software.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USB1OTGLPEN : USB1OTG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USB1ULPILPEN : USB_PHY1 clock enable during CSleep mode Set and reset by software.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DCMI_PSSILPEN : digital camera interface peripheral clock enable during CSleep mode (DCMI or PSSI depending which IP is active) Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRYPTLPEN : CRYPT peripheral clock enable during CSleep mode Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HASHLPEN : HASH peripheral clock enable during CSleep mode Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RNGLPEN : RNG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDMMC2LPEN : SDMMC2 and SDMMC2 delay clock enable during CSleep mode Set and reset by software.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFSDMDMALPEN : DFSDMDMA clock enable during CSleep mode Set and reset by software.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AHBSRAM1LPEN : AHBSRAM1 clock enable during CSleep mode Set and reset by software.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AHBSRAM2LPEN : AHBSRAM2 clock enable during CSleep mode Set and reset by software.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOALPEN : GPIOA peripheral clock enable during CSleep mode Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOBLPEN : GPIOB peripheral clock enable during CSleep mode Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOCLPEN : GPIOC peripheral clock enable during CSleep mode Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIODLPEN : GPIOD peripheral clock enable during CSleep mode Set and reset by software.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOELPEN : GPIOE peripheral clock enable during CSleep mode Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOFLPEN : GPIOF peripheral clock enable during CSleep mode Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOGLPEN : GPIOG peripheral clock enable during CSleep mode Set and reset by software.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOHLPEN : GPIOH peripheral clock enable during CSleep mode Set and reset by software.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOILPEN : GPIOI peripheral clock enable during CSleep mode Set and reset by software.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOJLPEN : GPIOJ peripheral clock enable during CSleep mode Set and reset by software.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOKLPEN : GPIOK peripheral clock enable during CSleep mode Set and reset by software.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BDMA2LPEN : SmartRun domain DMA and DMAMUX clock enable during CSleep mode Set and reset by software.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKPRAMLPEN : Backup RAM clock enable during CSleep mode Set and reset by software.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRDSRAMLPEN : SmartRun domain SRAM clock enable during CSleep mode Set and reset by software.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LTDCLPEN : LTDC peripheral clock enable during CSleep mode Set and reset by software. The LTDC peripheral clocks are the kernel clock provided to ltdc_ker_ck input and the rcc_pclk3 bus interface clock.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WWDGLPEN : WWDG clock enable during CSleep mode Set and reset by software.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM2LPEN : TIM2 peripheral clock enable during CSleep mode Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM3LPEN : TIM3 peripheral clock enable during CSleep mode Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM4LPEN : TIM4 peripheral clock enable during CSleep mode Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM5LPEN : TIM5 peripheral clock enable during CSleep mode Set and reset by software.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM6LPEN : TIM6 peripheral clock enable during CSleep mode Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM7LPEN : TIM7 peripheral clock enable during CSleep mode Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM12LPEN : TIM12 peripheral clock enable during CSleep mode Set and reset by software.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM13LPEN : TIM13 peripheral clock enable during CSleep mode Set and reset by software.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM14LPEN : TIM14 peripheral clock enable during CSleep mode Set and reset by software.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPTIM1LPEN : LPTIM1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2LPEN : SPI2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI3LPEN : SPI3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPDIFRXLPEN : SPDIFRX peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFRXSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART2LPEN : USART2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART3LPEN : USART3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART4LPEN : UART4 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART5LPEN : UART5 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART5 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1LPEN : I2C1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C1 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C2LPEN : I2C2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C2 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C3LPEN : I2C3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C3 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CECLPEN : HDMI-CEC peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the HDMI-CEC are the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAC1LPEN : DAC1 (containing two converters) peripheral clock enable during CSleep mode Set and reset by software.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART7LPEN : UART7 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART7 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART8LPEN : UART8 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART8 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRSLPEN : clock recovery system peripheral clock enable during CSleep mode Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWPMILPEN : SWPMI peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SWPMI are the kernel clock selected by SWPMISEL and provided to swpmi_ker_ck input, and the rcc_pclk1 bus interface clock.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPAMPLPEN : OPAMP peripheral clock enable during CSleep mode Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MDIOSLPEN : MDIOS peripheral clock enable during CSleep mode Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDCANLPEN : FDCAN peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the FDCAN are: the kernel clock selected by FDCANSEL and provided to fdcan_clk input, and the rcc_pclk1 bus interface clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM1LPEN : TIM1 peripheral clock enable during CSleep mode Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM8LPEN : TIM8 peripheral clock enable during CSleep mode Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART1LPEN : USART1 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck inputs, and the rcc_pclk2 bus interface clock.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART6LPEN : USART6 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART9LPEN : UART9 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USART10LPEN : USART10 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1LPEN : SPI1 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI4LPEN : SPI4 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM15LPEN : TIM15 peripheral clock enable during CSleep mode Set and reset by software.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM16LPEN : TIM16 peripheral clock enable during CSleep mode Set and reset by software.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM17LPEN : TIM17 peripheral clock enable during CSleep mode Set and reset by software.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI5LPEN : SPI5 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAI1LPEN : SAI1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAI2LPEN : SAI2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI23EL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFSDM1LPEN : DFSDM1 peripheral clocks enable during CSleep mode Set and reset by software. DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCFGLPEN : SYSCFG peripheral clock enable during CSleep mode Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPUART1LPEN : LPUART1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI6LPEN : SPI6 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C4LPEN : I2C4 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPTIM2LPEN : LPTIM2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPTIM3LPEN : LPTIM3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAC2LPEN : DAC2 (containing one converter) peripheral clock enable during CSleep mode Set and reset by software.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMP12LPEN : COMP1 and 2 peripheral clock enable during CSleep mode Set and reset by software.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VREFLPEN : VREF peripheral clock enable during CSleep mode Set and reset by software.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCAPBLPEN : RTC APB clock enable during CSleep mode Set and reset by software.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTSLPEN : temperature sensor peripheral clock enable during CSleep mode Set and reset by software.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFSDM2LPEN : DFSDM2 peripheral clock enable during CSleep mode Set and reset by software.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.