\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
DBGMCU Identity Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : Device ID
bits : 0 - 11 (12 bit)
REV_ID : Revision
bits : 16 - 31 (16 bit)
DBGMCU APB3 peripheral freeze register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDG : WWDG stop in debug
bits : 6 - 6 (1 bit)
DBGMCU APB1L peripheral freeze register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2 : TIM2 stop in debug
bits : 0 - 0 (1 bit)
TIM3 : TIM3 stop in debug
bits : 1 - 1 (1 bit)
TIM4 : TIM4 stop in debug
bits : 2 - 2 (1 bit)
TIM5 : TIM5 stop in debug
bits : 3 - 3 (1 bit)
TIM6 : TIM6 stop in debug
bits : 4 - 4 (1 bit)
TIM7 : TIM7 stop in debug
bits : 5 - 5 (1 bit)
TIM12 : TIM12 stop in debug
bits : 6 - 6 (1 bit)
TIM13 : TIM13 stop in debug
bits : 7 - 7 (1 bit)
TIM14 : TIM14 stop in debug
bits : 8 - 8 (1 bit)
LPTIM1 : LPTIM1 stop in debug
bits : 9 - 9 (1 bit)
I2C1 : I2C1 SMBUS timeout stop in debug
bits : 21 - 21 (1 bit)
I2C2 : I2C2 SMBUS timeout stop in debug
bits : 22 - 22 (1 bit)
I2C3 : I2C3 SMBUS timeout stop in debug
bits : 23 - 23 (1 bit)
DBGMCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSLEEP_CD : Allow D1 domain debug in Sleep mode
bits : 0 - 0 (1 bit)
DBGSTOP_CD : Allow D1 domain debug in Stop mode
bits : 1 - 1 (1 bit)
DBGSTBY_CD : Allow D1 domain debug in Standby mode
bits : 2 - 2 (1 bit)
DBGSTOP_SRD : debug in SmartRun domain Stop mode
bits : 7 - 7 (1 bit)
DBGSTBY_SRD : debug in SmartRun domain Standby mode
bits : 8 - 8 (1 bit)
TRACECLKEN : Trace port clock enable
bits : 20 - 20 (1 bit)
CDDBGCKEN : CPU domain debug clock enable
bits : 21 - 21 (1 bit)
SRDDBGCKEN : SmartRun domain debug clock enable
bits : 22 - 22 (1 bit)
TRGOEN : External trigger output enable
bits : 28 - 28 (1 bit)
DBGMCU APB2 peripheral freeze register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1 : TIM1 stop in debug
bits : 0 - 0 (1 bit)
TIM8 : TIM8 stop in debug
bits : 1 - 1 (1 bit)
TIM15 : TIM15 stop in debug
bits : 16 - 16 (1 bit)
TIM16 : TIM16 stop in debug
bits : 17 - 17 (1 bit)
TIM17 : TIM17 stop in debug
bits : 18 - 18 (1 bit)
DBGMCU APB4 peripheral freeze register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C4 : I2C4 SMBUS timeout stop in debug
bits : 7 - 7 (1 bit)
LPTIM2 : LPTIM2 stop in debug
bits : 9 - 9 (1 bit)
LPTIM3 : LPTIM3 stop in debug
bits : 10 - 10 (1 bit)
RTC : RTC stop in debug
bits : 16 - 16 (1 bit)
WDGLSCD : LS watchdog for CPU domain stop in debug
bits : 18 - 18 (1 bit)
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