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DBGMCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

IDC

APB3FZ1

APB1LFZ1

CR

APB2FZ1

APB4FZ1


IDC

DBGMCU Identity Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDC IDC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device ID
bits : 0 - 11 (12 bit)

REV_ID : Revision
bits : 16 - 31 (16 bit)


APB3FZ1

DBGMCU APB3 peripheral freeze register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3FZ1 APB3FZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDG

WWDG : WWDG stop in debug
bits : 6 - 6 (1 bit)


APB1LFZ1

DBGMCU APB1L peripheral freeze register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LFZ1 APB1LFZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 LPTIM1 I2C1 I2C2 I2C3

TIM2 : TIM2 stop in debug
bits : 0 - 0 (1 bit)

TIM3 : TIM3 stop in debug
bits : 1 - 1 (1 bit)

TIM4 : TIM4 stop in debug
bits : 2 - 2 (1 bit)

TIM5 : TIM5 stop in debug
bits : 3 - 3 (1 bit)

TIM6 : TIM6 stop in debug
bits : 4 - 4 (1 bit)

TIM7 : TIM7 stop in debug
bits : 5 - 5 (1 bit)

TIM12 : TIM12 stop in debug
bits : 6 - 6 (1 bit)

TIM13 : TIM13 stop in debug
bits : 7 - 7 (1 bit)

TIM14 : TIM14 stop in debug
bits : 8 - 8 (1 bit)

LPTIM1 : LPTIM1 stop in debug
bits : 9 - 9 (1 bit)

I2C1 : I2C1 SMBUS timeout stop in debug
bits : 21 - 21 (1 bit)

I2C2 : I2C2 SMBUS timeout stop in debug
bits : 22 - 22 (1 bit)

I2C3 : I2C3 SMBUS timeout stop in debug
bits : 23 - 23 (1 bit)


CR

DBGMCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGSLEEP_CD DBGSTOP_CD DBGSTBY_CD DBGSTOP_SRD DBGSTBY_SRD TRACECLKEN CDDBGCKEN SRDDBGCKEN TRGOEN

DBGSLEEP_CD : Allow D1 domain debug in Sleep mode
bits : 0 - 0 (1 bit)

DBGSTOP_CD : Allow D1 domain debug in Stop mode
bits : 1 - 1 (1 bit)

DBGSTBY_CD : Allow D1 domain debug in Standby mode
bits : 2 - 2 (1 bit)

DBGSTOP_SRD : debug in SmartRun domain Stop mode
bits : 7 - 7 (1 bit)

DBGSTBY_SRD : debug in SmartRun domain Standby mode
bits : 8 - 8 (1 bit)

TRACECLKEN : Trace port clock enable
bits : 20 - 20 (1 bit)

CDDBGCKEN : CPU domain debug clock enable
bits : 21 - 21 (1 bit)

SRDDBGCKEN : SmartRun domain debug clock enable
bits : 22 - 22 (1 bit)

TRGOEN : External trigger output enable
bits : 28 - 28 (1 bit)


APB2FZ1

DBGMCU APB2 peripheral freeze register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2FZ1 APB2FZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1 TIM8 TIM15 TIM16 TIM17

TIM1 : TIM1 stop in debug
bits : 0 - 0 (1 bit)

TIM8 : TIM8 stop in debug
bits : 1 - 1 (1 bit)

TIM15 : TIM15 stop in debug
bits : 16 - 16 (1 bit)

TIM16 : TIM16 stop in debug
bits : 17 - 17 (1 bit)

TIM17 : TIM17 stop in debug
bits : 18 - 18 (1 bit)


APB4FZ1

DBGMCU APB4 peripheral freeze register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB4FZ1 APB4FZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C4 LPTIM2 LPTIM3 RTC WDGLSCD

I2C4 : I2C4 SMBUS timeout stop in debug
bits : 7 - 7 (1 bit)

LPTIM2 : LPTIM2 stop in debug
bits : 9 - 9 (1 bit)

LPTIM3 : LPTIM3 stop in debug
bits : 10 - 10 (1 bit)

RTC : RTC stop in debug
bits : 16 - 16 (1 bit)

WDGLSCD : LS watchdog for CPU domain stop in debug
bits : 18 - 18 (1 bit)



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