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LPTIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ISR

CR

CMP

ARR

CNT

ICR

IER

CFGR


ISR

Interrupt and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPM ARRM EXTTRIG CMPOK ARROK UP DOWN

CMPM : Compare match
bits : 0 - 0 (1 bit)

ARRM : Autoreload match
bits : 1 - 1 (1 bit)

EXTTRIG : External trigger edge event
bits : 2 - 2 (1 bit)

CMPOK : Compare register update OK
bits : 3 - 3 (1 bit)

ARROK : Autoreload register update OK
bits : 4 - 4 (1 bit)

UP : Counter direction change down to up
bits : 5 - 5 (1 bit)

DOWN : Counter direction change up to down
bits : 6 - 6 (1 bit)


CR

Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SNGSTRT CNTSTRT

ENABLE : LPTIM Enable
bits : 0 - 0 (1 bit)

SNGSTRT : LPTIM start in single mode
bits : 1 - 1 (1 bit)

CNTSTRT : Timer start in continuous mode
bits : 2 - 2 (1 bit)


CMP

Compare Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : Compare value.
bits : 0 - 15 (16 bit)


ARR

Autoreload Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARR ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : Auto reload value.
bits : 0 - 15 (16 bit)


CNT

Counter Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value.
bits : 0 - 15 (16 bit)


ICR

Interrupt Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMCF ARRMCF EXTTRIGCF CMPOKCF ARROKCF UPCF DOWNCF

CMPMCF : compare match Clear Flag
bits : 0 - 0 (1 bit)

ARRMCF : Autoreload match Clear Flag
bits : 1 - 1 (1 bit)

EXTTRIGCF : External trigger valid edge Clear Flag
bits : 2 - 2 (1 bit)

CMPOKCF : Compare register update OK Clear Flag
bits : 3 - 3 (1 bit)

ARROKCF : Autoreload register update OK Clear Flag
bits : 4 - 4 (1 bit)

UPCF : Direction change to UP Clear Flag
bits : 5 - 5 (1 bit)

DOWNCF : Direction change to down Clear Flag
bits : 6 - 6 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMIE ARRMIE EXTTRIGIE CMPOKIE ARROKIE UPIE DOWNIE

CMPMIE : Compare match Interrupt Enable
bits : 0 - 0 (1 bit)

ARRMIE : Autoreload match Interrupt Enable
bits : 1 - 1 (1 bit)

EXTTRIGIE : External trigger valid edge Interrupt Enable
bits : 2 - 2 (1 bit)

CMPOKIE : Compare register update OK Interrupt Enable
bits : 3 - 3 (1 bit)

ARROKIE : Autoreload register update OK Interrupt Enable
bits : 4 - 4 (1 bit)

UPIE : Direction change to UP Interrupt Enable
bits : 5 - 5 (1 bit)

DOWNIE : Direction change to down Interrupt Enable
bits : 6 - 6 (1 bit)


CFGR

Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSEL CKPOL CKFLT TRGFLT PRESC TRIGSEL TRIGEN TIMOUT WAVE WAVPOL PRELOAD COUNTMODE ENC

CKSEL : Clock selector
bits : 0 - 0 (1 bit)

CKPOL : Clock Polarity
bits : 1 - 2 (2 bit)

CKFLT : Configurable digital filter for external clock
bits : 3 - 4 (2 bit)

TRGFLT : Configurable digital filter for trigger
bits : 6 - 7 (2 bit)

PRESC : Clock prescaler
bits : 9 - 11 (3 bit)

TRIGSEL : Trigger selector
bits : 13 - 15 (3 bit)

TRIGEN : Trigger enable and polarity
bits : 17 - 18 (2 bit)

TIMOUT : Timeout enable
bits : 19 - 19 (1 bit)

WAVE : Waveform shape
bits : 20 - 20 (1 bit)

WAVPOL : Waveform shape polarity
bits : 21 - 21 (1 bit)

PRELOAD : Registers update mode
bits : 22 - 22 (1 bit)

COUNTMODE : counter mode enabled
bits : 23 - 23 (1 bit)

ENC : Encoder mode enable
bits : 24 - 24 (1 bit)



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