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SCB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x41 byte (0x0)
mem_usage : registers
protection :

Registers

CPUID

SCR

CCR

SHPR2

SHPR3

ICSR

VTOR

AIRCR


CPUID

CPUID base register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPUID CPUID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Revision PartNo Architecture Variant Implementer

Revision : Revision number
bits : 0 - 3 (4 bit)

PartNo : Part number of the processor
bits : 4 - 15 (12 bit)

Architecture : Reads as 0xF
bits : 16 - 19 (4 bit)

Variant : Variant number
bits : 20 - 23 (4 bit)

Implementer : Implementer code
bits : 24 - 31 (8 bit)


SCR

System control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPONEXIT SLEEPDEEP SEVEONPEND

SLEEPONEXIT : SLEEPONEXIT
bits : 1 - 1 (1 bit)

SLEEPDEEP : SLEEPDEEP
bits : 2 - 2 (1 bit)

SEVEONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)


CCR

Configuration and control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONBASETHRDENA USERSETMPEND UNALIGN__TRP DIV_0_TRP BFHFNMIGN STKALIGN

NONBASETHRDENA : Configures how the processor enters Thread mode
bits : 0 - 0 (1 bit)

USERSETMPEND : USERSETMPEND
bits : 1 - 1 (1 bit)

UNALIGN__TRP : UNALIGN_ TRP
bits : 3 - 3 (1 bit)

DIV_0_TRP : DIV_0_TRP
bits : 4 - 4 (1 bit)

BFHFNMIGN : BFHFNMIGN
bits : 8 - 8 (1 bit)

STKALIGN : STKALIGN
bits : 9 - 9 (1 bit)


SHPR2

System handler priority registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR2 SHPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_11

PRI_11 : Priority of system handler 11
bits : 24 - 31 (8 bit)


SHPR3

System handler priority registers
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR3 SHPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_14 PRI_15

PRI_14 : Priority of system handler 14
bits : 16 - 23 (8 bit)

PRI_15 : Priority of system handler 15
bits : 24 - 31 (8 bit)


ICSR

Interrupt control and state register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSR ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTACTIVE RETTOBASE VECTPENDING ISRPENDING PENDSTCLR PENDSTSET PENDSVCLR PENDSVSET NMIPENDSET

VECTACTIVE : Active vector
bits : 0 - 8 (9 bit)

RETTOBASE : Return to base level
bits : 11 - 11 (1 bit)

VECTPENDING : Pending vector
bits : 12 - 18 (7 bit)

ISRPENDING : Interrupt pending flag
bits : 22 - 22 (1 bit)

PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 25 (1 bit)

PENDSTSET : SysTick exception set-pending bit
bits : 26 - 26 (1 bit)

PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)

PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)

NMIPENDSET : NMI set-pending bit.
bits : 31 - 31 (1 bit)


VTOR

Vector table offset register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTOR VTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBLOFF

TBLOFF : Vector table base offset field
bits : 7 - 31 (25 bit)


AIRCR

Application interrupt and reset control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AIRCR AIRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTCLRACTIVE SYSRESETREQ ENDIANESS VECTKEYSTAT

VECTCLRACTIVE : VECTCLRACTIVE
bits : 1 - 1 (1 bit)

SYSRESETREQ : SYSRESETREQ
bits : 2 - 2 (1 bit)

ENDIANESS : ENDIANESS
bits : 15 - 15 (1 bit)

VECTKEYSTAT : Register key
bits : 16 - 31 (16 bit)



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