qorvo PAC52XX 2024.05.04 ARM 32-bit Cortex-M0 Microcontroller based device, with analog and digital peripherals for motor and power control CM0 r0p0 little 2 true 8 32 ADC Analog to Digital Converter ADC 0x0 0x0 0x1000 registers n IRQ_ADC 13 ADCCR ADC conversion result register 0xC read-only n 0x0 0x0 ADCRESULT ADC conversion result 0 15 ADCCTL ADC control register 0x8 read-write n 0x0 0x0 ADCBUSY ADC busy 7 read-only no operation ADC not busy 0 busy ADC conversion or auto sequencer active 1 ADCCDIV ADC input clock FCLK divider 0 2 FCLK /1 FCLK divided by 1 0 FCLK /2 FCLK divided by 2 1 FCLK /3 FCLK divided by 3 2 FCLK /4 FCLK divided by 4 3 FCLK /5 FCLK divided by 5 4 FCLK /6 FCLK divided by 6 5 FCLK /7 FCLK divided by 7 6 FCLK /8 FCLK divided by 8 7 ADCEN ADC Module Enable 15 disabled turn off ADC module 0 enabled enable ADC module 1 ADCMODE ADC conversion mode 10 2 single single channel 0 AUTO0 automated sequence 0 only 1 AUTO1 automated sequencer 1 only 2 AUTO01 automated sequencer 0 and 1 daisy chained 3 AUTO0TRIG automated sequencer 0 only trigger condition 4 AUTO1TRIG automated sequencer 1 only trigger condition 5 AUTO01TRIG automated sequencer 0 and 1 daisy chained trigger 6 AUTO01TRIGIND automated sequencer 0 and 1 independently triggered 7 ADCMUX ADC MUX input select 4 2 AD0 AD0 input 0 AD2 AD2 input 2 AD3 AD3 input 3 AD4 AD4 input 4 AD5 AD5 input 5 VSSA VSSA input 7 ADCSTART Start ADC Conversion 14 stop stop ADC conversion 0 start start ADC conversion 1 ADCINT ADC interrupt register 0x10 read-write n 0x0 0x0 ADCINT ADC conversion finished interrupt 0 none no interrupt 0 interrupt interrupt, write 1b to clear 1 ADCINT_EN ADC conversion finished interrupt enabled 8 disabled interrupt disabled 0 enabled interrupt enabled 1 AS0INT Auto sequencer 0 conversions finished interrupt 2 none no interrupt 0 interrupt interrupt, write 1b to clear 1 AS0INT_EN Enable auto sequencer 0 conversions finished interrupt 10 disabled interrupt disabled 0 enabled interrupt enabled 1 AS1INT Auto sequencer 1 conversions finished interrupt 3 none no interrupt 0 interrupt interrupt, write 1b to clear 1 AS1INT_EN Enable auto sequencer 1 conversions finished interrupt 11 disabled interrupt disabled 0 enabled interrupt enabled 1 ASCINT Auto sequencer collision interrupt 4 none no interrupt 0 interrupt interrupt, write 1b to clear 1 ASCINTSEQ Last auto sequencer to trigger ADCINT.ASCINT 16 1 none no trigger 0 AS0 auto sequencer 0 triggered interrupt 1 AS1 Auto sequencer 1 triggered interrupt 2 both Both auto sequencer 0 and 1 triggered interrupt 3 ASCINTTR Last auto sequencer to run 18 1 none no sequencer ran 0 AS0 auto sequencer 0 last ran 1 AS1 Auto sequencer 1 last ran 2 ASCINT_EN Enable auto sequencer collision interrupt 12 disabled interrupt disabled 0 enabled interrupt enabled 1 EMUXINT EMUX data transfer finished interrupt 1 none no interrupt 0 interrupt interrupt, write 1b to clear 1 EMUXINT_EN EMUX transfer finished interrupt enabled 9 disabled interrupt disabled 0 enabled interrupt enabled 1 AS0CTL Auto sequencer 0 control register 0x40 read-write n 0x0 0x0 ASAxTRPWM Auto sequencer PWM trigger source 0 3 PWMA0 PWMA0 Trigger 0 PWMA1 PWMA1 Trigger 1 PWMC0 PWMC0 10 PWMC1 PWMC1 11 PWMD0 PWMD0 12 PWMD1 PWMD1 13 PWMA2 PWMA2 Trigger 2 PWMA3 PWMA3 Trigger 3 PWMA4 PWMA4 Trigger 4 PWMA5 PWMA5 Trigger 5 PWMA6 PWMA6 Trigger 6 PWMA7 PWMA7 Trigger 7 PWMB0 PWMB0 8 PWMB1 PWMB1 9 ASAxTRTMR Auto sequencer timer trigger source 4 1 Timer A Timer A 0 Timer B Timer B 1 Timer C Timer C 2 Timer D Timer D 3 ASxBUSY Auto sequencer busy 12 not busy auto sequencer not active 0 busy auto sequencer sampling active 1 ASxD Auto sequencer sampling depth 8 2 1 1 sample 0 2 2 samples 1 3 3 samples 2 4 4 samples 3 5 5 samples 4 6 6 samples 5 7 7 samples 6 8 8 samples 7 ASxEN Auto sequencer enabled 11 disabled auto sequencer disabled 0 enabled auto sequencer enabled 1 ASxTR Auto sequencer trigger source 7 PWM PWM, as defined by ASxCTL.ASxTRPWM 0 Timer Timer, as defined by ASxCTL.ASxTRTMR 1 ASxTRE Auto sequencer trigger source ASxCTL.ASxTR edge 6 highToLow High to low edge 0 lowToHigh Low to high edge 1 AS0R0 Auto sequencer 0 sample 0 result register 0x48 read-write n 0x0 0x0 ADCRESULT ADC conversion result 0 9 AS0R1 Auto sequencer 0 sample 1 result register 0x50 read-write n 0x0 0x0 AS0R2 Auto sequencer 0 sample 2 result register 0x58 read-write n 0x0 0x0 AS0R3 Auto sequencer 0 sample 3 result register 0x60 read-write n 0x0 0x0 AS0R4 Auto sequencer 0 sample 4 result register 0x68 read-write n 0x0 0x0 AS0R5 Auto sequencer 0 sample 5 result register 0x70 read-write n 0x0 0x0 AS0R6 Auto sequencer 0 sample 6 result register 0x78 read-write n 0x0 0x0 AS0R7 Auto sequencer 0 sample 7 result register 0x80 read-write n 0x0 0x0 AS0S0 Auto sequencer 0 sample 0 control register 0x44 read-write n 0x0 0x0 ADCMUX ADC MUX input select 12 2 EMUX EMUX 0 AD2 AD2 2 AD3 AD3 3 AD4 AD4 4 AD5 AD5 5 VSSA VSSA 7 DELAY Delay between start of sample sequence and start of ADC conversion in input clocks 10 1 0 0 ADC input clocks 0 4 4 ADC input clocks 1 8 8 ADC input clocks 2 16 16 ADC input clocks 3 EMUXD EMUXD 0 7 EMUXS EMUX transmission start 8 1 none Do not send data 0 before Send EMUXD data at beginning of this sample sequence 1 end Send EMUXD data after S/H of ADC 2 AS0S1 Auto sequencer 0 sample 1 control register 0x4C read-write n 0x0 0x0 AS0S2 Auto sequencer 0 sample 2 control register 0x54 read-write n 0x0 0x0 AS0S3 Auto sequencer 0 sample 3 control register 0x5C read-write n 0x0 0x0 AS0S4 Auto sequencer 0 sample 4 control register 0x64 read-write n 0x0 0x0 AS0S5 Auto sequencer 0 sample 5 control register 0x6C read-write n 0x0 0x0 AS0S6 Auto sequencer 0 sample 6 control register 0x74 read-write n 0x0 0x0 AS0S7 Auto sequencer 0 sample 7 control register 0x7C read-write n 0x0 0x0 AS1CTL Auto sequencer 1 control register 0x100 read-write n 0x0 0x0 ASAxTRPWM Auto sequencer PWM trigger source 0 3 PWMA0 PWMA0 0 PWMA1 PWMA1 1 PWMC0 PWMC0 10 PWMC1 PWMC1 11 PWMD0 PWMD0 12 PWMD1 PWMD1 13 PWMA2 PWMA2 2 PWMA3 PWMA3 3 PWMA4 PWMA4 4 PWMA5 PWMA5 5 PWMA6 PWMA6 6 PWMA7 PWMA7 7 PWMB0 PWMB0 8 PWMB1 PWMB1 9 ASAxTRTMR Auto sequencer timer trigger source 4 1 Timer A Timer A 0 Timer B Timer B 1 Timer C Timer C 2 Timer D Timer D 3 ASxBUSY Auto sequencer busy 12 not busy auto sequencer not active 0 busy auto sequencer sampling active 1 ASxD Auto sequencer sampling depth 8 2 1 1 sample 0 2 2 samples 1 3 3 samples 2 4 4 samples 3 5 5 samples 4 6 6 samples 5 7 7 samples 6 8 8 samples 7 ASxEN Auto sequencer enabled 11 disabled auto sequencer disabled 0 enabled auto sequencer enabled 1 ASxTR Auto sequencer trigger source 7 PWM PWM, as defined by ASxCTL.ASxTRPWM 0 Timer Timer, as defined by ASxCTL.ASxTRTMR 1 ASxTRE Auto sequencer trigger source ASxCTL.ASxTR edge 6 highToLow High to low edge 0 lowToHigh Low to high edge 1 AS1R0 Auto sequencer 1 sample 0 result register 0x108 read-write n 0x0 0x0 ADCRESULT ADC conversion result 0 9 AS1R1 Auto sequencer 1 sample 1 result register 0x110 read-write n 0x0 0x0 AS1R2 Auto sequencer 1 sample 2 result register 0x118 read-write n 0x0 0x0 AS1R3 Auto sequencer 1 sample 3 result register 0x120 read-write n 0x0 0x0 AS1R4 Auto sequencer 1 sample 4 result register 0x128 read-write n 0x0 0x0 AS1R5 Auto sequencer 1 sample 5 result register 0x130 read-write n 0x0 0x0 AS1R6 Auto sequencer 1 sample 6 result register 0x138 read-write n 0x0 0x0 AS1R7 Auto sequencer 1 sample 7 result register 0x140 read-write n 0x0 0x0 AS1S0 Auto sequencer 1 sample 0 control register 0x104 read-write n 0x0 0x0 ADCMUX ADC MUX input select 12 2 EMUX EMUX 0 AD2 AD2 2 AD3 AD3 3 AD4 AD4 4 AD5 AD5 5 VSSA VSSA 7 DELAY Delay between start of sample sequence and start of ADC conversion in input clocks 10 1 0 0 ADC input clocks 0 4 4 ADC input clocks 1 8 8 ADC input clocks 2 16 16 ADC input clocks 3 EMUXD EMUXD 0 7 EMUXS EMUX transmission start 8 1 none Do not send data 0 before Send EMUXD data at beginning of this sample sequence 1 end Send EMUXD data after S/H of ADC 2 AS1S1 Auto sequencer 1 sample 1 control register 0x10C read-write n 0x0 0x0 AS1S2 Auto sequencer 1 sample 2 control register 0x114 read-write n 0x0 0x0 AS1S3 Auto sequencer 1 sample 3 control register 0x11C read-write n 0x0 0x0 AS1S4 Auto sequencer 1 sample 4 control register 0x124 read-write n 0x0 0x0 AS1S5 Auto sequencer 1 sample 5 control register 0x12C read-write n 0x0 0x0 AS1S6 Auto sequencer 1 sample 6 control register 0x134 read-write n 0x0 0x0 AS1S7 Auto sequencer 1 sample 7 control register 0x13C read-write n 0x0 0x0 EMUXCTL ADC External MUX control register 0x0 read-write n 0x0 0x0 EMUXBUSY ADC External MUX status 4 busy ADC External MUX busy 0 not busy ADC External MUX not busy 1 EMUXC ADC External MUX control 5 manual ADC External MUX manual control 0 auto ADC External MUX controlled by auto-sequencer unit 1 EMUXCDIV ADC External MUX clock to FCLK divider 0 2 FCLK /1 FCLK dvided by 1 0 FCLK /2 FCLK dvided by 2 1 FCLK /3 FCLK dvided by 3 2 FCLK /4 FCLK dvided by 4 3 FCLK /5 FCLK dvided by 5 4 FCLK /6 FCLK dvided by 6 5 FCLK /7 FCLK dvided by 7 6 FCLK /8 FCLK dvided by 8 7 EMUXDONE ADC External MUX data send done 3 busy ADC External MUX busy 0 data sent ADC External MUX data sent 1 EMUXDATA ADC External MUX data register 0x4 read-write n 0x0 0x0 DATA ADC External MUX data register 0 15 GPIOA General-Purpose Input-Output Port A GPIOA 0x0 0x0 0x40 registers n IRQ_GPIOA 3 DS GPIO Port Output Drive Strength Select 0x8 read-write n 0x0 0x0 P0 Port output drive strength select 0 0 low Low output drive strength selected 0 high High output drive strength selected 1 P1 Port output drive strength select 1 1 low Low output drive strength selected 0 high High output drive strength selected 1 P2 Port output drive strength select 2 2 low Low output drive strength selected 0 high High output drive strength selected 1 P3 Port output drive strength select 3 3 low Low output drive strength selected 0 high High output drive strength selected 1 P4 Port output drive strength select 4 4 low Low output drive strength selected 0 high High output drive strength selected 1 P5 Port output drive strength select 5 5 low Low output drive strength selected 0 high High output drive strength selected 1 P6 Port output drive strength select 6 6 low Low output drive strength selected 0 high High output drive strength selected 1 P7 Port output drive strength select 7 7 low Low output drive strength selected 0 high High output drive strength selected 1 IN GPIO Port Input 0x14 read-only n 0x0 0x0 P0 Port0 input state 0 low Logic low 0 high Logic high 1 P1 Port1 input state 1 low Logic low 0 high Logic high 1 P2 Port2 input state 2 low Logic low 0 high Logic high 1 P3 Port3 input state 3 low Logic low 0 high Logic high 1 P4 Port4 input state 4 low Logic low 0 high Logic high 1 P5 Port5 input state 5 low Logic low 0 high Logic high 1 P6 Port6 input state 6 low Logic low 0 high Logic high 1 P7 Port7 input state 7 low Logic low 0 high Logic high 1 INTE GPIO Port Interrupt Enable 0x24 read-write n 0x0 0x0 P0 Port0 Interrupt Enable 0 disable Disable interrupt 0 enable Enable interrupt 1 P1 Port1 Interrupt Enable 1 disable Disable interrupt 0 enable Enable interrupt 1 P2 Port2 Interrupt Enable 2 disable Disable interrupt 0 enable Enable interrupt 1 P3 Port3 Interrupt Enable 3 disable Disable interrupt 0 enable Enable interrupt 1 P4 Port4 Interrupt Enable 4 disable Disable interrupt 0 enable Enable interrupt 1 P5 Port5 Interrupt Enable 5 disable Disable interrupt 0 enable Enable interrupt 1 P6 Port6 Interrupt Enable 6 disable Disable interrupt 0 enable Enable interrupt 1 P7 Port7 Interrupt Enable 7 disable Disable interrupt 0 enable Enable interrupt 1 INTF GPIO Port Interrupt Flag 0x28 -1 read-writeOnce n 0x0 0x0 P0 Port0 Interrupt 0 none No interrupt pending 0 interrupt Interrupt pending 1 P1 Port1 Interrupt 1 none No interrupt pending 0 interrupt Interrupt pending 1 P2 Port2 Interrupt 2 none No interrupt pending 0 interrupt Interrupt pending 1 P3 Port3 Interrupt 3 none No interrupt pending 0 interrupt Interrupt pending 1 P4 Port4 Interrupt 4 none No interrupt pending 0 interrupt Interrupt pending 1 P5 Port5 Interrupt 5 none No interrupt pending 0 interrupt Interrupt pending 1 P6 Port6 Interrupt 6 none No interrupt pending 0 interrupt Interrupt pending 1 P7 Port7 Interrupt 7 none No interrupt pending 0 interrupt Interrupt pending 1 INTM GPIO Port Interrupt Mask 0x2C read-write n 0x0 0x0 P0 Port0 Interrupt Mask 0 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P1 Port1 Interrupt Mask 1 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P2 Port2 Interrupt Mask 2 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P3 Port3 Interrupt Mask 3 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P4 Port4 Interrupt Mask 4 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P5 Port5 Interrupt Mask 5 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P6 Port6 Interrupt Mask 6 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P7 Port7 Interrupt Mask 7 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 INTP GPIO Port Interrupt Polarity 0x20 read-write n 0x0 0x0 P0 Port0 Interrupt Polarity 0 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P1 Port1 Interrupt Polarity 1 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P2 Port2 Interrupt Polarity 2 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P3 Port3 Interrupt Polarity 3 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P4 Port4 Interrupt Polarity 4 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P5 Port5 Interrupt Polarity 5 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P6 Port6 Interrupt Polarity 6 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P7 Port7 Interrupt Polarity 7 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 OUT GPIO Port Output 0x0 read-write n 0x0 0x0 P0 Port output 0 0 low Set output low if GPIOn->OUTEN.P0 = 1 0 high Set output high if GPIOn->OUTEN.P0 = 1 1 P1 Port output 1 1 low Set output low if GPIOn->OUTEN.P1 = 1 0 high Set output high if GPIOn->OUTEN.P1 = 1 1 P2 Port output 2 2 low Set output low if GPIOn->OUTEN.P2 = 1 0 high Set output high if GPIOn->OUTEN.P2 = 1 1 P3 Port output 3 3 low Set output low if GPIOn->OUTEN.P3 = 1 0 high Set output high if GPIOn->OUTEN.P3 = 1 1 P4 Port output 4 4 low Set output low if GPIOn->OUTEN.P4 = 1 0 high Set output high if GPIOn->OUTEN.P4 = 1 1 P5 Port output 5 5 low Set output low if GPIOn->OUTEN.P5 = 1 0 high Set output high if GPIOn->OUTEN.P5 = 1 1 P6 Port output 6 6 low Set output low if GPIOn->OUTEN.P6 = 1 0 high Set output high if GPIOn->OUTEN.P6 = 1 1 P7 Port output 7 7 low Set output low if GPIOn->OUTEN.P7 = 1 0 high Set output high if GPIOn->OUTEN.P7 = 1 1 OUTEN GPIO Port Output Enable 0x4 read-write n 0x0 0x0 P0 Port output enable 0 0 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P0 1 P1 Port output enable 1 1 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P1 1 P2 Port output enable 2 2 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P2 1 P3 Port output enable 3 3 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P3 1 P4 Port output enable 4 4 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P4 1 P5 Port output enable 5 5 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P5 1 P6 Port output enable 6 6 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P6 1 P7 Port output enable 7 7 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P7 1 PD GPIO Port Weak Pull Down 0x10 read-write n 0x0 0x0 P0 Port0 weak pull-down select 0 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P1 Port1 weak pull-down select 1 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P2 Port2 weak pull-down select 2 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P3 Port3 weak pull-down select 3 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P4 Port4 weak pull-down select 4 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P5 Port0 weak pull-down select 5 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P6 Port6 weak pull-down select 6 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P7 Port7 weak pull-down select 7 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 PSEL GPIO Peripheral Select 0x1C read-write n 0x0 0x0 P0 Port0 peripheral select 0 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P1 Port1 peripheral select 2 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P2 Port2 peripheral select 4 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P3 Port3 peripheral select 6 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P4 Port4 peripheral select 8 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P5 Port5 peripheral select 10 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P6 Port6 peripheral select 12 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P7 Port7 peripheral select 14 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 PU GPIO Port Weak Pull Up 0xC read-write n 0x0 0x0 P0 Port0 weak pull-up select 0 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P1 Port1 weak pull-up select 1 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P2 Port2 weak pull-up select 2 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P3 Port3 weak pull-up select 3 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P4 Port4 weak pull-up select 4 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P5 Port5 weak pull-up select 5 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P6 Port6 weak pull-up select 6 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P7 Port7 weak pull-up select 7 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 GPIOB General-Purpose Input-Output Port B GPIOA 0x0 0x0 0x40 registers n IRQ_GPIOB 4 DS GPIO Port Output Drive Strength Select 0x8 read-write n 0x0 0x0 P0 Port output drive strength select 0 0 low Low output drive strength selected 0 high High output drive strength selected 1 P1 Port output drive strength select 1 1 low Low output drive strength selected 0 high High output drive strength selected 1 P2 Port output drive strength select 2 2 low Low output drive strength selected 0 high High output drive strength selected 1 P3 Port output drive strength select 3 3 low Low output drive strength selected 0 high High output drive strength selected 1 P4 Port output drive strength select 4 4 low Low output drive strength selected 0 high High output drive strength selected 1 P5 Port output drive strength select 5 5 low Low output drive strength selected 0 high High output drive strength selected 1 P6 Port output drive strength select 6 6 low Low output drive strength selected 0 high High output drive strength selected 1 P7 Port output drive strength select 7 7 low Low output drive strength selected 0 high High output drive strength selected 1 IN GPIO Port Input 0x14 read-only n 0x0 0x0 P0 Port0 input state 0 low Logic low 0 high Logic high 1 P1 Port1 input state 1 low Logic low 0 high Logic high 1 P2 Port2 input state 2 low Logic low 0 high Logic high 1 P3 Port3 input state 3 low Logic low 0 high Logic high 1 P4 Port4 input state 4 low Logic low 0 high Logic high 1 P5 Port5 input state 5 low Logic low 0 high Logic high 1 P6 Port6 input state 6 low Logic low 0 high Logic high 1 P7 Port7 input state 7 low Logic low 0 high Logic high 1 INTE GPIO Port Interrupt Enable 0x24 read-write n 0x0 0x0 P0 Port0 Interrupt Enable 0 disable Disable interrupt 0 enable Enable interrupt 1 P1 Port1 Interrupt Enable 1 disable Disable interrupt 0 enable Enable interrupt 1 P2 Port2 Interrupt Enable 2 disable Disable interrupt 0 enable Enable interrupt 1 P3 Port3 Interrupt Enable 3 disable Disable interrupt 0 enable Enable interrupt 1 P4 Port4 Interrupt Enable 4 disable Disable interrupt 0 enable Enable interrupt 1 P5 Port5 Interrupt Enable 5 disable Disable interrupt 0 enable Enable interrupt 1 P6 Port6 Interrupt Enable 6 disable Disable interrupt 0 enable Enable interrupt 1 P7 Port7 Interrupt Enable 7 disable Disable interrupt 0 enable Enable interrupt 1 INTF GPIO Port Interrupt Flag 0x28 -1 read-writeOnce n 0x0 0x0 P0 Port0 Interrupt 0 none No interrupt pending 0 interrupt Interrupt pending 1 P1 Port1 Interrupt 1 none No interrupt pending 0 interrupt Interrupt pending 1 P2 Port2 Interrupt 2 none No interrupt pending 0 interrupt Interrupt pending 1 P3 Port3 Interrupt 3 none No interrupt pending 0 interrupt Interrupt pending 1 P4 Port4 Interrupt 4 none No interrupt pending 0 interrupt Interrupt pending 1 P5 Port5 Interrupt 5 none No interrupt pending 0 interrupt Interrupt pending 1 P6 Port6 Interrupt 6 none No interrupt pending 0 interrupt Interrupt pending 1 P7 Port7 Interrupt 7 none No interrupt pending 0 interrupt Interrupt pending 1 INTM GPIO Port Interrupt Mask 0x2C read-write n 0x0 0x0 P0 Port0 Interrupt Mask 0 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P1 Port1 Interrupt Mask 1 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P2 Port2 Interrupt Mask 2 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P3 Port3 Interrupt Mask 3 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P4 Port4 Interrupt Mask 4 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P5 Port5 Interrupt Mask 5 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P6 Port6 Interrupt Mask 6 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P7 Port7 Interrupt Mask 7 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 INTP GPIO Port Interrupt Polarity 0x20 read-write n 0x0 0x0 P0 Port0 Interrupt Polarity 0 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P1 Port1 Interrupt Polarity 1 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P2 Port2 Interrupt Polarity 2 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P3 Port3 Interrupt Polarity 3 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P4 Port4 Interrupt Polarity 4 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P5 Port5 Interrupt Polarity 5 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P6 Port6 Interrupt Polarity 6 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P7 Port7 Interrupt Polarity 7 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 OUT GPIO Port Output 0x0 read-write n 0x0 0x0 P0 Port output 0 0 low Set output low if GPIOn->OUTEN.P0 = 1 0 high Set output high if GPIOn->OUTEN.P0 = 1 1 P1 Port output 1 1 low Set output low if GPIOn->OUTEN.P1 = 1 0 high Set output high if GPIOn->OUTEN.P1 = 1 1 P2 Port output 2 2 low Set output low if GPIOn->OUTEN.P2 = 1 0 high Set output high if GPIOn->OUTEN.P2 = 1 1 P3 Port output 3 3 low Set output low if GPIOn->OUTEN.P3 = 1 0 high Set output high if GPIOn->OUTEN.P3 = 1 1 P4 Port output 4 4 low Set output low if GPIOn->OUTEN.P4 = 1 0 high Set output high if GPIOn->OUTEN.P4 = 1 1 P5 Port output 5 5 low Set output low if GPIOn->OUTEN.P5 = 1 0 high Set output high if GPIOn->OUTEN.P5 = 1 1 P6 Port output 6 6 low Set output low if GPIOn->OUTEN.P6 = 1 0 high Set output high if GPIOn->OUTEN.P6 = 1 1 P7 Port output 7 7 low Set output low if GPIOn->OUTEN.P7 = 1 0 high Set output high if GPIOn->OUTEN.P7 = 1 1 OUTEN GPIO Port Output Enable 0x4 read-write n 0x0 0x0 P0 Port output enable 0 0 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P0 1 P1 Port output enable 1 1 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P1 1 P2 Port output enable 2 2 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P2 1 P3 Port output enable 3 3 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P3 1 P4 Port output enable 4 4 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P4 1 P5 Port output enable 5 5 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P5 1 P6 Port output enable 6 6 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P6 1 P7 Port output enable 7 7 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P7 1 PD GPIO Port Weak Pull Down 0x10 read-write n 0x0 0x0 P0 Port0 weak pull-down select 0 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P1 Port1 weak pull-down select 1 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P2 Port2 weak pull-down select 2 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P3 Port3 weak pull-down select 3 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P4 Port4 weak pull-down select 4 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P5 Port0 weak pull-down select 5 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P6 Port6 weak pull-down select 6 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P7 Port7 weak pull-down select 7 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 PSEL GPIO Peripheral Select 0x1C read-write n 0x0 0x0 P0 Port0 peripheral select 0 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P1 Port1 peripheral select 2 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P2 Port2 peripheral select 4 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P3 Port3 peripheral select 6 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P4 Port4 peripheral select 8 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P5 Port5 peripheral select 10 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P6 Port6 peripheral select 12 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P7 Port7 peripheral select 14 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 PU GPIO Port Weak Pull Up 0xC read-write n 0x0 0x0 P0 Port0 weak pull-up select 0 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P1 Port1 weak pull-up select 1 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P2 Port2 weak pull-up select 2 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P3 Port3 weak pull-up select 3 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P4 Port4 weak pull-up select 4 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P5 Port5 weak pull-up select 5 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P6 Port6 weak pull-up select 6 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P7 Port7 weak pull-up select 7 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 GPIOC General-Purpose Input-Output Port C GPIOC 0x0 0x0 0x40 registers n IRQ_GPIOC 5 IN GPIO Port Input 0x14 read-only n 0x0 0x0 P0 Port0 input state 0 low Logic low 0 high Logic high 1 P1 Port1 input state 1 low Logic low 0 high Logic high 1 P2 Port2 input state 2 low Logic low 0 high Logic high 1 P3 Port3 input state 3 low Logic low 0 high Logic high 1 P4 Port4 input state 4 low Logic low 0 high Logic high 1 P5 Port5 input state 5 low Logic low 0 high Logic high 1 P6 Port6 input state 6 low Logic low 0 high Logic high 1 P7 Port7 input state 7 low Logic low 0 high Logic high 1 INE GPIO Port Input Enable 0x18 read-write n 0x0 0x0 P0 Port input enable 0 0 disabled Input disabled 0 enabled Input enabled, for I/O operation 1 P1 Port input enable 1 1 disabled Input disabled 0 enabled Input enabled, for I/O operation 1 P2 Port input enable 2 2 disabled Input disabled 0 high Input enabled, for I/O operation 1 P3 Port input enable 3 3 disabled Input disabled 0 enabled Input enabled, for I/O operation 1 P4 Port input enable 4 4 disabled Input disabled 0 enabled Input enabled, for I/O operation 1 P5 Port input enable 5 5 disabled Input disabled 0 enabled Input enabled, for I/O operation 1 P6 Port input enable 6 6 disabled Input disabled 0 enabled Input enabled, for I/O operation 1 P7 Port input enable 7 7 disabled Input disabled 0 enabled Input enabled, for I/O operation 1 INTE GPIO Port Interrupt Enable 0x24 read-write n 0x0 0x0 P0 Port0 Interrupt Enable 0 disable Disable interrupt 0 enable Enable interrupt 1 P1 Port1 Interrupt Enable 1 disable Disable interrupt 0 enable Enable interrupt 1 P2 Port2 Interrupt Enable 2 disable Disable interrupt 0 enable Enable interrupt 1 P3 Port3 Interrupt Enable 3 disable Disable interrupt 0 enable Enable interrupt 1 P4 Port4 Interrupt Enable 4 disable Disable interrupt 0 enable Enable interrupt 1 P5 Port5 Interrupt Enable 5 disable Disable interrupt 0 enable Enable interrupt 1 P6 Port6 Interrupt Enable 6 disable Disable interrupt 0 enable Enable interrupt 1 P7 Port7 Interrupt Enable 7 disable Disable interrupt 0 enable Enable interrupt 1 INTF GPIO Port Interrupt Flag 0x28 -1 read-writeOnce n 0x0 0x0 P0 Port0 Interrupt 0 none No interrupt pending 0 interrupt Interrupt pending 1 P1 Port1 Interrupt 1 none No interrupt pending 0 interrupt Interrupt pending 1 P2 Port2 Interrupt 2 none No interrupt pending 0 interrupt Interrupt pending 1 P3 Port3 Interrupt 3 none No interrupt pending 0 interrupt Interrupt pending 1 P4 Port4 Interrupt 4 none No interrupt pending 0 interrupt Interrupt pending 1 P5 Port5 Interrupt 5 none No interrupt pending 0 interrupt Interrupt pending 1 P6 Port6 Interrupt 6 none No interrupt pending 0 interrupt Interrupt pending 1 P7 Port7 Interrupt 7 none No interrupt pending 0 interrupt Interrupt pending 1 INTM GPIO Port Interrupt Mask 0x2C read-write n 0x0 0x0 P0 Port0 Interrupt Mask 0 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P1 Port1 Interrupt Mask 1 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P2 Port2 Interrupt Mask 2 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P3 Port3 Interrupt Mask 3 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P4 Port4 Interrupt Mask 4 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P5 Port5 Interrupt Mask 5 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P6 Port6 Interrupt Mask 6 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P7 Port7 Interrupt Mask 7 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 INTP GPIO Port Interrupt Polarity 0x20 read-write n 0x0 0x0 P0 Port0 Interrupt Polarity 0 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P1 Port1 Interrupt Polarity 1 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P2 Port2 Interrupt Polarity 2 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P3 Port3 Interrupt Polarity 3 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P4 Port4 Interrupt Polarity 4 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P5 Port5 Interrupt Polarity 5 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P6 Port6 Interrupt Polarity 6 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P7 Port7 Interrupt Polarity 7 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 OUT GPIO Port Output 0x0 read-write n 0x0 0x0 P0 Port output 0 0 low Set output low if GPIOn->OUTEN.P0 = 1 0 high Set output high if GPIOn->OUTEN.P0 = 1 1 P1 Port output 1 1 low Set output low if GPIOn->OUTEN.P1 = 1 0 high Set output high if GPIOn->OUTEN.P1 = 1 1 P2 Port output 2 2 low Set output low if GPIOn->OUTEN.P2 = 1 0 high Set output high if GPIOn->OUTEN.P2 = 1 1 P3 Port output 3 3 low Set output low if GPIOn->OUTEN.P3 = 1 0 high Set output high if GPIOn->OUTEN.P3 = 1 1 P4 Port output 4 4 low Set output low if GPIOn->OUTEN.P4 = 1 0 high Set output high if GPIOn->OUTEN.P4 = 1 1 P5 Port output 5 5 low Set output low if GPIOn->OUTEN.P5 = 1 0 high Set output high if GPIOn->OUTEN.P5 = 1 1 P6 Port output 6 6 low Set output low if GPIOn->OUTEN.P6 = 1 0 high Set output high if GPIOn->OUTEN.P6 = 1 1 P7 Port output 7 7 low Set output low if GPIOn->OUTEN.P7 = 1 0 high Set output high if GPIOn->OUTEN.P7 = 1 1 OUTEN GPIO Port Output Enable 0x4 read-write n 0x0 0x0 P0 Port output enable 0 0 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P0 1 P1 Port output enable 1 1 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P1 1 P2 Port output enable 2 2 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P2 1 P3 Port output enable 3 3 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P3 1 P4 Port output enable 4 4 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P4 1 P5 Port output enable 5 5 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P5 1 P6 Port output enable 6 6 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P6 1 P7 Port output enable 7 7 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P7 1 GPIOD General-Purpose Input-Output Port D GPIOA 0x0 0x0 0x40 registers n IRQ_GPIOD 6 DS GPIO Port Output Drive Strength Select 0x8 read-write n 0x0 0x0 P0 Port output drive strength select 0 0 low Low output drive strength selected 0 high High output drive strength selected 1 P1 Port output drive strength select 1 1 low Low output drive strength selected 0 high High output drive strength selected 1 P2 Port output drive strength select 2 2 low Low output drive strength selected 0 high High output drive strength selected 1 P3 Port output drive strength select 3 3 low Low output drive strength selected 0 high High output drive strength selected 1 P4 Port output drive strength select 4 4 low Low output drive strength selected 0 high High output drive strength selected 1 P5 Port output drive strength select 5 5 low Low output drive strength selected 0 high High output drive strength selected 1 P6 Port output drive strength select 6 6 low Low output drive strength selected 0 high High output drive strength selected 1 P7 Port output drive strength select 7 7 low Low output drive strength selected 0 high High output drive strength selected 1 IN GPIO Port Input 0x14 read-only n 0x0 0x0 P0 Port0 input state 0 low Logic low 0 high Logic high 1 P1 Port1 input state 1 low Logic low 0 high Logic high 1 P2 Port2 input state 2 low Logic low 0 high Logic high 1 P3 Port3 input state 3 low Logic low 0 high Logic high 1 P4 Port4 input state 4 low Logic low 0 high Logic high 1 P5 Port5 input state 5 low Logic low 0 high Logic high 1 P6 Port6 input state 6 low Logic low 0 high Logic high 1 P7 Port7 input state 7 low Logic low 0 high Logic high 1 INTE GPIO Port Interrupt Enable 0x24 read-write n 0x0 0x0 P0 Port0 Interrupt Enable 0 disable Disable interrupt 0 enable Enable interrupt 1 P1 Port1 Interrupt Enable 1 disable Disable interrupt 0 enable Enable interrupt 1 P2 Port2 Interrupt Enable 2 disable Disable interrupt 0 enable Enable interrupt 1 P3 Port3 Interrupt Enable 3 disable Disable interrupt 0 enable Enable interrupt 1 P4 Port4 Interrupt Enable 4 disable Disable interrupt 0 enable Enable interrupt 1 P5 Port5 Interrupt Enable 5 disable Disable interrupt 0 enable Enable interrupt 1 P6 Port6 Interrupt Enable 6 disable Disable interrupt 0 enable Enable interrupt 1 P7 Port7 Interrupt Enable 7 disable Disable interrupt 0 enable Enable interrupt 1 INTF GPIO Port Interrupt Flag 0x28 -1 read-writeOnce n 0x0 0x0 P0 Port0 Interrupt 0 none No interrupt pending 0 interrupt Interrupt pending 1 P1 Port1 Interrupt 1 none No interrupt pending 0 interrupt Interrupt pending 1 P2 Port2 Interrupt 2 none No interrupt pending 0 interrupt Interrupt pending 1 P3 Port3 Interrupt 3 none No interrupt pending 0 interrupt Interrupt pending 1 P4 Port4 Interrupt 4 none No interrupt pending 0 interrupt Interrupt pending 1 P5 Port5 Interrupt 5 none No interrupt pending 0 interrupt Interrupt pending 1 P6 Port6 Interrupt 6 none No interrupt pending 0 interrupt Interrupt pending 1 P7 Port7 Interrupt 7 none No interrupt pending 0 interrupt Interrupt pending 1 INTM GPIO Port Interrupt Mask 0x2C read-write n 0x0 0x0 P0 Port0 Interrupt Mask 0 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P1 Port1 Interrupt Mask 1 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P2 Port2 Interrupt Mask 2 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P3 Port3 Interrupt Mask 3 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P4 Port4 Interrupt Mask 4 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P5 Port5 Interrupt Mask 5 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P6 Port6 Interrupt Mask 6 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P7 Port7 Interrupt Mask 7 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 INTP GPIO Port Interrupt Polarity 0x20 read-write n 0x0 0x0 P0 Port0 Interrupt Polarity 0 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P1 Port1 Interrupt Polarity 1 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P2 Port2 Interrupt Polarity 2 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P3 Port3 Interrupt Polarity 3 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P4 Port4 Interrupt Polarity 4 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P5 Port5 Interrupt Polarity 5 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P6 Port6 Interrupt Polarity 6 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P7 Port7 Interrupt Polarity 7 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 OUT GPIO Port Output 0x0 read-write n 0x0 0x0 P0 Port output 0 0 low Set output low if GPIOn->OUTEN.P0 = 1 0 high Set output high if GPIOn->OUTEN.P0 = 1 1 P1 Port output 1 1 low Set output low if GPIOn->OUTEN.P1 = 1 0 high Set output high if GPIOn->OUTEN.P1 = 1 1 P2 Port output 2 2 low Set output low if GPIOn->OUTEN.P2 = 1 0 high Set output high if GPIOn->OUTEN.P2 = 1 1 P3 Port output 3 3 low Set output low if GPIOn->OUTEN.P3 = 1 0 high Set output high if GPIOn->OUTEN.P3 = 1 1 P4 Port output 4 4 low Set output low if GPIOn->OUTEN.P4 = 1 0 high Set output high if GPIOn->OUTEN.P4 = 1 1 P5 Port output 5 5 low Set output low if GPIOn->OUTEN.P5 = 1 0 high Set output high if GPIOn->OUTEN.P5 = 1 1 P6 Port output 6 6 low Set output low if GPIOn->OUTEN.P6 = 1 0 high Set output high if GPIOn->OUTEN.P6 = 1 1 P7 Port output 7 7 low Set output low if GPIOn->OUTEN.P7 = 1 0 high Set output high if GPIOn->OUTEN.P7 = 1 1 OUTEN GPIO Port Output Enable 0x4 read-write n 0x0 0x0 P0 Port output enable 0 0 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P0 1 P1 Port output enable 1 1 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P1 1 P2 Port output enable 2 2 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P2 1 P3 Port output enable 3 3 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P3 1 P4 Port output enable 4 4 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P4 1 P5 Port output enable 5 5 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P5 1 P6 Port output enable 6 6 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P6 1 P7 Port output enable 7 7 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P7 1 PD GPIO Port Weak Pull Down 0x10 read-write n 0x0 0x0 P0 Port0 weak pull-down select 0 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P1 Port1 weak pull-down select 1 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P2 Port2 weak pull-down select 2 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P3 Port3 weak pull-down select 3 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P4 Port4 weak pull-down select 4 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P5 Port0 weak pull-down select 5 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P6 Port6 weak pull-down select 6 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P7 Port7 weak pull-down select 7 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 PSEL GPIO Peripheral Select 0x1C read-write n 0x0 0x0 P0 Port0 peripheral select 0 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P1 Port1 peripheral select 2 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P2 Port2 peripheral select 4 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P3 Port3 peripheral select 6 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P4 Port4 peripheral select 8 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P5 Port5 peripheral select 10 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P6 Port6 peripheral select 12 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P7 Port7 peripheral select 14 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 PU GPIO Port Weak Pull Up 0xC read-write n 0x0 0x0 P0 Port0 weak pull-up select 0 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P1 Port1 weak pull-up select 1 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P2 Port2 weak pull-up select 2 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P3 Port3 weak pull-up select 3 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P4 Port4 weak pull-up select 4 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P5 Port5 weak pull-up select 5 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P6 Port6 weak pull-up select 6 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P7 Port7 weak pull-up select 7 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 GPIOE General-Purpose Input-Output Port E GPIOA 0x0 0x0 0x40 registers n IRQ_GPIOE 7 DS GPIO Port Output Drive Strength Select 0x8 read-write n 0x0 0x0 P0 Port output drive strength select 0 0 low Low output drive strength selected 0 high High output drive strength selected 1 P1 Port output drive strength select 1 1 low Low output drive strength selected 0 high High output drive strength selected 1 P2 Port output drive strength select 2 2 low Low output drive strength selected 0 high High output drive strength selected 1 P3 Port output drive strength select 3 3 low Low output drive strength selected 0 high High output drive strength selected 1 P4 Port output drive strength select 4 4 low Low output drive strength selected 0 high High output drive strength selected 1 P5 Port output drive strength select 5 5 low Low output drive strength selected 0 high High output drive strength selected 1 P6 Port output drive strength select 6 6 low Low output drive strength selected 0 high High output drive strength selected 1 P7 Port output drive strength select 7 7 low Low output drive strength selected 0 high High output drive strength selected 1 IN GPIO Port Input 0x14 read-only n 0x0 0x0 P0 Port0 input state 0 low Logic low 0 high Logic high 1 P1 Port1 input state 1 low Logic low 0 high Logic high 1 P2 Port2 input state 2 low Logic low 0 high Logic high 1 P3 Port3 input state 3 low Logic low 0 high Logic high 1 P4 Port4 input state 4 low Logic low 0 high Logic high 1 P5 Port5 input state 5 low Logic low 0 high Logic high 1 P6 Port6 input state 6 low Logic low 0 high Logic high 1 P7 Port7 input state 7 low Logic low 0 high Logic high 1 INTE GPIO Port Interrupt Enable 0x24 read-write n 0x0 0x0 P0 Port0 Interrupt Enable 0 disable Disable interrupt 0 enable Enable interrupt 1 P1 Port1 Interrupt Enable 1 disable Disable interrupt 0 enable Enable interrupt 1 P2 Port2 Interrupt Enable 2 disable Disable interrupt 0 enable Enable interrupt 1 P3 Port3 Interrupt Enable 3 disable Disable interrupt 0 enable Enable interrupt 1 P4 Port4 Interrupt Enable 4 disable Disable interrupt 0 enable Enable interrupt 1 P5 Port5 Interrupt Enable 5 disable Disable interrupt 0 enable Enable interrupt 1 P6 Port6 Interrupt Enable 6 disable Disable interrupt 0 enable Enable interrupt 1 P7 Port7 Interrupt Enable 7 disable Disable interrupt 0 enable Enable interrupt 1 INTF GPIO Port Interrupt Flag 0x28 -1 read-writeOnce n 0x0 0x0 P0 Port0 Interrupt 0 none No interrupt pending 0 interrupt Interrupt pending 1 P1 Port1 Interrupt 1 none No interrupt pending 0 interrupt Interrupt pending 1 P2 Port2 Interrupt 2 none No interrupt pending 0 interrupt Interrupt pending 1 P3 Port3 Interrupt 3 none No interrupt pending 0 interrupt Interrupt pending 1 P4 Port4 Interrupt 4 none No interrupt pending 0 interrupt Interrupt pending 1 P5 Port5 Interrupt 5 none No interrupt pending 0 interrupt Interrupt pending 1 P6 Port6 Interrupt 6 none No interrupt pending 0 interrupt Interrupt pending 1 P7 Port7 Interrupt 7 none No interrupt pending 0 interrupt Interrupt pending 1 INTM GPIO Port Interrupt Mask 0x2C read-write n 0x0 0x0 P0 Port0 Interrupt Mask 0 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P1 Port1 Interrupt Mask 1 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P2 Port2 Interrupt Mask 2 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P3 Port3 Interrupt Mask 3 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P4 Port4 Interrupt Mask 4 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P5 Port5 Interrupt Mask 5 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P6 Port6 Interrupt Mask 6 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 P7 Port7 Interrupt Mask 7 disabled Disable interrupt mask 0 enabled Enable interrupt mask 1 INTP GPIO Port Interrupt Polarity 0x20 read-write n 0x0 0x0 P0 Port0 Interrupt Polarity 0 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P1 Port1 Interrupt Polarity 1 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P2 Port2 Interrupt Polarity 2 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P3 Port3 Interrupt Polarity 3 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P4 Port4 Interrupt Polarity 4 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P5 Port5 Interrupt Polarity 5 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P6 Port6 Interrupt Polarity 6 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 P7 Port7 Interrupt Polarity 7 falling Falling edge, high to low transition 0 rising Rising edge, low to high transition 1 OUT GPIO Port Output 0x0 read-write n 0x0 0x0 P0 Port output 0 0 low Set output low if GPIOn->OUTEN.P0 = 1 0 high Set output high if GPIOn->OUTEN.P0 = 1 1 P1 Port output 1 1 low Set output low if GPIOn->OUTEN.P1 = 1 0 high Set output high if GPIOn->OUTEN.P1 = 1 1 P2 Port output 2 2 low Set output low if GPIOn->OUTEN.P2 = 1 0 high Set output high if GPIOn->OUTEN.P2 = 1 1 P3 Port output 3 3 low Set output low if GPIOn->OUTEN.P3 = 1 0 high Set output high if GPIOn->OUTEN.P3 = 1 1 P4 Port output 4 4 low Set output low if GPIOn->OUTEN.P4 = 1 0 high Set output high if GPIOn->OUTEN.P4 = 1 1 P5 Port output 5 5 low Set output low if GPIOn->OUTEN.P5 = 1 0 high Set output high if GPIOn->OUTEN.P5 = 1 1 P6 Port output 6 6 low Set output low if GPIOn->OUTEN.P6 = 1 0 high Set output high if GPIOn->OUTEN.P6 = 1 1 P7 Port output 7 7 low Set output low if GPIOn->OUTEN.P7 = 1 0 high Set output high if GPIOn->OUTEN.P7 = 1 1 OUTEN GPIO Port Output Enable 0x4 read-write n 0x0 0x0 P0 Port output enable 0 0 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P0 1 P1 Port output enable 1 1 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P1 1 P2 Port output enable 2 2 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P2 1 P3 Port output enable 3 3 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P3 1 P4 Port output enable 4 4 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P4 1 P5 Port output enable 5 5 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P5 1 P6 Port output enable 6 6 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P6 1 P7 Port output enable 7 7 low Output disabled, high-impedance state 0 high Output state set by GPIOn->OUT.P7 1 PD GPIO Port Weak Pull Down 0x10 read-write n 0x0 0x0 P0 Port0 weak pull-down select 0 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P1 Port1 weak pull-down select 1 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P2 Port2 weak pull-down select 2 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P3 Port3 weak pull-down select 3 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P4 Port4 weak pull-down select 4 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P5 Port0 weak pull-down select 5 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P6 Port6 weak pull-down select 6 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 P7 Port7 weak pull-down select 7 disabled Weak pull-down disabled 0 enabled Weak pull-down to VSS enabled 1 PSEL GPIO Peripheral Select 0x1C read-write n 0x0 0x0 P0 Port0 peripheral select 0 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P1 Port1 peripheral select 2 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P2 Port2 peripheral select 4 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P3 Port3 peripheral select 6 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P4 Port4 peripheral select 8 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P5 Port5 peripheral select 10 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P6 Port6 peripheral select 12 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 P7 Port7 peripheral select 14 1 IO Port in I/O mode 0 Peripheral 1 Peripheral Configuration 1 1 Peripheral 2 Peripheral Configuration 2 2 Peripheral 3 Peripheral Configuration 3 3 PU GPIO Port Weak Pull Up 0xC read-write n 0x0 0x0 P0 Port0 weak pull-up select 0 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P1 Port1 weak pull-up select 1 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P2 Port2 weak pull-up select 2 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P3 Port3 weak pull-up select 3 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P4 Port4 weak pull-up select 4 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P5 Port5 weak pull-up select 5 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P6 Port6 weak pull-up select 6 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 P7 Port7 weak pull-up select 7 disabled Weak pull-up disabled 0 enabled Weak pull-up to VCCIO enabled 1 I2C I2C I2C 0x0 0x0 0x1000 registers n IRQ_I2C 17 I2CBAUD I2C baud rate 0x40 read-write n 0x0 0x0 SCLH Number of HCLK cycles for I2CCCL high time 16 10 SCLL Number of HCLK cycles for I2CCL low time 0 10 I2CCFG I2C Configuration Register 0x0 -1 read-write n 0x0 0x0 ADDRMODE Address Mode 4 7-bit 7-bit addressing 0 10-bit 10-bit addressing 1 MAEN Master Enable 2 disable I2C master disable 0 enable I2C Master enable 1 SLEN Slave Enable 0 disable I2C Slave disable 0 enable I2C Slave enable 1 I2CINT I2C Interrupt 0x4 read-only n 0x0 0x0 MAADDRACKINT Master address acknowledged 9 ACK Master address ACK'd 0 NACK Master address NACK'd, cleared on read 1 MAARBLINT Master lost arbitration 10 false no error 0 true Master lost arbitration, clear on read 1 MACTLE MACCTL access register accessed 1 false I2CMACTL not accessed by I2C engine since last read of I2CINT 0 true I2CMACTL processed by I2C engine, clears on read 1 MADACKINT Master data acknowledge 11 ACK Master data ACK'd 0 NACK Master data NACK'd, cleared on read 1 MARXF Master receive data register MARXDATA full 2 false MARXDATA did not receive data since last read of I2CINT 0 true MARXDATA received data from I2C bus, cleared on read 1 MATXE Master transmit data register MATXDATA empty 0 not transmitted MATXDATA not transmitted since last read of I2CINT 0 transmitted MATXDATA transmitted to I2C bus, clears on read 1 MAXFERDONEINT Master transfer complete 8 false not done 0 true Master transfer complete, cleared on read 1 SLADDRMINT Slave address match 16 none no match 0 match Slave address match detected, cleared on read 1 SLRXFINT Slave receive data register SLRXDATA full 18 false SLRXDATA did not receive data since last read of I2CINT 0 true SLRXDATA received data from I2C bus, cleared on read 1 SLTXEINT Slave transmit data register SLTXDATA empty 17 false SLTXDATA not transmitted since last read of I2CINT 0 true SLTXDATA transmitted to I2C bus, cleared on read 1 SLXFERDONEINT Slave transfer done interrupt 24 false Slave transfer not completed 0 true Slave transfer complete, cleared on read 1 I2CINTEN I2C Interrupt Enable 0x8 read-write n 0x0 0x0 MACTLE MACTLE interrupt enable 1 disabled interrupt disabled 0 enabled interrupt enabled 1 MARXF MARXF interrupt enable 2 disabled interrupt disabled 0 enabled interrupt enabled 1 MATXE MATXE interrupt enable 0 disabled interrupt disabled 0 enabled interrupt enabled 1 MAXFERDONE MAXFERDONE interrupt enable 8 disabled interrupt disabled 0 enabled interrupt enabled 1 SLADDRM SLADDRM interrupt enable 16 disabled interrupt disabled 0 enabled interrupt enabled 1 SLRXF SLRXF interrupt enable 18 disabled interrupt disabled 0 enabled interrupt enabled 1 SLTXE SLTXE interrupt enable 17 disabled interrupt disabled 0 enabled interrupt enabled 1 SLXFERDONEINTEN SLXFERDONEINTEN interrupt enable 24 disabled interrupt disabled 0 enabled interrupt enabled 1 I2CMACTL I2C master access control 0x30 read-write n 0x0 0x0 I2CADDRL Lower I2C address bits 6:0 0 6 I2CADDRU Upper I2C address bits 9:7 7 2 I2CMACTLF I2CMACTL full 13 not full I2CMACTL processed, write allowed 0 full I2CMACTL full, write not allowed, cleared on read 1 RSTART Repeated start 10 no STOP at end of transfer 0 yes No STOP at end of transfer, repeated START 1 XFERTYPE Master transfer type 11 write I2C Master write 0 read I2C Master read 1 I2CMARXDATA I2C master receive data 0x34 read-write n 0x0 0x0 I2CMARXDATAF I2CMARXDATA full 8 read-only empty I2CMARXDATA register empty 0 full I2CMARXDATA register full, cleared on read 1 MARXDATA Master data byte received 0 7 I2CMATXDATA I2C master transmit data 0x38 read-write n 0x0 0x0 I2CMATXDATAF I2CMATXDATA full 8 read-only empty I2CMATXDATA register empty 0 full I2CMATXDATA register full, cleared on read 1 LBYTE Last byte of transfer 9 false not last byte of transfer 0 true last byte of READ or WRITE indicator, initiate STOP after data transfer 1 MATXDATA Master data byte to transmit 0 7 I2CSLADDR I2C slave address 0x78 read-write n 0x0 0x0 SLADDRH Higher slave address bits9:7 7 2 SLADDRL Lower slave address bits 6:0 0 6 I2CSLRXDATA I2C slave receive data 0x70 read-write n 0x0 0x0 I2CSLRXDATAF I2CSLRXDATA full 8 read-only empty I2CSLRXDATA register empty 0 full I2CSLRXDATA register full, data not transmitted 1 SLRXDATA Slave data byte received 0 7 I2CSLTXDATA I2C slave receive data 0x74 read-write n 0x0 0x0 I2CSLTXDATAF I2CSLTXDATA full 9 read-only empty I2CSLTXDATA register empty 0 full I2CSLTXDATA register full, data not transmitted 1 NACK Slave ACK or NACK 8 ACK Issue ACK on I2C write 0 NACK Issue NACK on I2C write 1 SLTXDATA Slave data byte to transmit 0 7 MEMCTL FLASH Memory Controller MEMCTL 0x0 0x0 0x1000 registers n IRQ_MEMCTL 0 FLASHBWRITE FLASH Buffered Write Data 0x2C read-write n 0x0 0x0 FLASHLOCK FLASH Lock Register 0x0 read-write n 0x0 0x0 FLASHPAGE FLASH page select register 0x8 read-write n 0x0 0x0 FLASHPERASE FLASH page erase register 0x14 read-write n 0x0 0x0 FLASHSTATUS FLASH Status Register 0x4 read-write n 0x0 0x0 PERASE Page Erase Active 1 inactive Page erase finished or no page erase in progress 0 active Page erase in progress 1 WRITE Buffered Write Active 0 inactive Buffered write inactive 0 active Buffered write active 1 FLASHWSTATE FLASH Wait State Register 0x28 read-write n 0x0 0x0 WSTATE FLASH access wait state 0 1 0 0 FLASH wait states 0 1 1 FLASH wait states 1 2 2 FLASH wait states 2 3 3 FLASH wait states 3 SWDACCESS SWD access status 0x24 read-write n 0x0 0x0 RTC Real-Time Clock RTC 0x0 0x0 0x1000 registers n IRQ_RTC 19 RTCCDV Real-Time Clock Count-down Value Register 0x4 -1 read-write n 0x0 0x0 KEY RTC register key 24 7 RSTVALUE 24b RTC count-down value 0 23 RTCCTL Real-Time Clock Control Register 0x0 -1 read-write n 0x0 0x0 KEY RTCCTL register key 24 7 RTCCLKDIV Real-Time Clock Input Clock Divider 6 3 /2 Real-Time clock divider: /2 0 /4 Real-Time clock divider: /4 1 /2048 Real-Time clock divider: /2048 10 /4096 Real-Time clock divider: /4096 11 /8192 Real-Time clock divider: /8192 12 /16384 Real-Time clock divider: /16384 13 /32768 Real-Time clock divider: /32768 14 /65536 Real-Time clock divider: /65536 15 /8 Real-Time clock divider: /8 2 /16 Real-Time clock divider: /16 3 /32 Real-Time clock divider: /32 4 /64 Real-Time clock divider: /64 5 /128 Real-Time clock divider: /128 6 /256 Real-Time clock divider: /256 7 /512 Real-Time clock divider: /512 8 /1024 Real-Time clock divider: /1024 9 RTCCTRRST Real-Time Clock Counter Reset 0 2 key RTCCTL Reset Key 5 RTCINT Real-Time Clock Interrupt Flag 4 read-only clear Real-Time Clock interrupt flag clear 0 set Real-Time Clock interrupt flag set 1 RTCINTEN Real-Time Clock Interrupt Enable 3 disabled Real-Time Clock interrupt disable 0 enabled Real-Time Clock interrupt enable 1 WRBUSY RTC register write busy 11 read-only not busy RTC register write not busy 0 busy RTC register write busy 1 RTCCTR Real-Time Clock Counter Register 0x8 -1 read-only n 0x0 0x0 SOCB SOC Bus Bridge SOCB 0x0 0x0 0x1000 registers n IRQ_SOCB 14 SOCBCFG SOC Bus Bridge Configuration 0x4 read-write n 0x0 0x0 MRST Module reset 2 disable do not hold the module in reset 0 reset force soft reset of module. The internal state machines are reset status register is cleared however, the soft reset does not affect control register values. 1 SOCBCTL SOC Bus Bridge Control 0x0 read-write n 0x0 0x0 MTRARM MTRANS re-arm 5 write-only re-arm re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE. 1 SIE SOC bus bridge interrupt enable 1 disable disable interrupts 0 enable enable interrupts 1 SSEN SOC bus bridge enable 0 disable disable this module 0 enable enable this module 1 SOCBD SOC Bus Bridge Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer 0x1C read-write n 0x0 0x0 DATA SOC bus bridge data 0 7 SOCBINT_EN SOC Bus Bridge Interrupt Enable 0x20 -1 read-write n 0x0 0x0 RDOFL_EN Read buffer overflow RDOFL interrupt enable 2 disable disable SOCBSTAT.RDOFL interrupt 0 enable enable SOCBSTAT.RDOFL interrupt 1 WRUFL_EN Write buffer underflow SOCBSTAT.WRUFL interrupt enable 8 disable disable SOCBSTAT.WRUFL interrupt 0 enable enable SOCBSTAT.WRUFL interrupt 1 SOCBSTAT SOC Bus Bridge Status 0x14 read-write n 0x0 0x0 CURSTATE Raw status of the SOC bus bridge master state machine's 'current_state' register 12 2 IDLE IDLE 0 CSSETUP CSSETUP 1 TRANSFER TRANSFER 2 CSHOLD CSHOLD 3 CSWAIT CSWAIT 4 CKWAIT CKWAIT 5 MTRANS MTRANS 6 CSBEGIN CSBEGIN 7 CYC_DONE Cycle done (current transfer is complete) 5 not done No cycle done detected since this bit was cleared 0 completed Cycle done detected, write one to clear 1 RDOFL Read buffer overflow 2 none no read overflow since bit cleared 0 overflow read overflow detected, write 1 to clear 1 RXFULL Receive holding register in use 10 empty RX incoming holding register contains no valid data word 0 full RX incoming holding register contains a valid data word 1 SOCB_INT SOC bus bridge interrupt 0 none no interrupt 0 interrupt interrupt 1 TXFULL Transmit holding register in use 9 ready TX transmit holding register ready to accept data word 0 not ready TX transmit holding register in use and not ready 1 WRUFL Write buffer underflow 8 none No write buffer underflow detected since this bit was cleared 0 underflow Write buffer underflow detected, write one to clear 1 SPI SPI SPI 0x0 0x0 0x1000 registers n IRQ_SPI 15 SPICFG SPI Configuration 0x4 read-write n 0x0 0x0 CP Master mode clock polarity 4 low SPICLK is low in it's inactive state 0 high SPICLK is high in it's inactive state 1 CPH Master mode clock phase 5 1st First clock transition of a new transfer is used to sample data 0 2nd Second clock transition of a new transfer is used to sample data 1 LB1ST Least bit first 3 MSB MSB is the first serial bit of transfer 0 LSB LSB is the first serial bit of transfer 1 MRST Module reset 2 disabled Do not hold module in reset 0 enabled Force soft reset of module 1 MTURBO Master turbo operation mode 11 disabled Legacy operation down to max 8:1 HCLK:SPICLK ratio 0 enabled Enable master turbo mode, using HCLK-based bit count allowing operation down to 2:1 HCLK:SPICLK ratio 1 RCVCP Slave mode clock polarity 6 low SPICLK is low in it's inactive state 0 high SPICLK is high in it's inactive state 1 RCVCPH Slave mode clock phase 7 1st First clock transition of a new transfer used to sample data 0 2nd Second clock transition of a new transfer used to sample data 1 TDBUF Transmit double-buffer mode 10 disabled Disable double-buffer, legacy operation with single shift register buffer 0 enabled Enable double-buffer 'ping-pong' on shift register transmit output path 1 TXDATPH Early transmit data phase 9 disabled Normal transmit data phase, transitions on launch edge of SPICLK 0 enabled MISO (slave) or MOSI (Master) transitions occur 1/2 a SPICLK period sooner than normal protocol 1 WL Word length 0 1 8 Word Length = 8-bits 0 16 Word Length = 16-bits 1 24 Word Length = 24-bits 2 32 Word Length = 32-bits 3 SPICLKDIV SPI Clock Divider 0x8 read-write n 0x0 0x0 CLKDIV Clock divisor for SCLK (HCLK / (CLKDIV + 1)*2) 0 15 SPICSSTR SPI Chip Select Steering Register 0x18 read-write n 0x0 0x0 CKWAIT SPI clock wait. Only applies if SPICTL.MTRANS=1b(multiple transfers with one chip select assertion). This value determines the minimum number of SPICLK periods to wait between back-to-back transfers. During this wait time, SPICLK does not toggle but CSx remains active. 20 3 CSHOLD Chip select hold. Minimum number of SPICLK periods to wait from the last SPICLK transition to de-assertion of CS 12 3 CSL Chip select active high level select 2 active-low Active-low outgoing (master) or incoming (slave) chip select 0 active-high Active-high outgoing (master) or incoming (slave) ship select 1 CSNUM Chip select number 0 1 SPICS0 SPICS0 0 SPICS1 SPICS1 1 SPICS2 SPICS2 2 CSSETUP Chip select setup. Minimum number of SPICLK periods to wait from assertion of CS to the first SPICLK transition 8 3 CSWAIT Chip select wait. The minimum number of SPICLK periods to wait between the de-assertion of CS and the re-assertion of CS 16 3 SPICTL SPI Control 0x0 read-write n 0x0 0x0 LPBK Internal loopback mode 2 disabled normal operation 0 enabled tie the serial out source to serial in internally (no IO buffers) 1 MMST_N Multi-master mode 7 enabled Multi-master mode 0 disabled Single master mode 1 MTRANS Multiple transfer mode 6 single Generate single transfers 0 multiple Generate multiple transfers 1 MTRARM MTRANS re-arm 5 write-only re-arm re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE. 1 RTRANS Auto-retrans on clock error 8 enabled Retransmit on clock error 0 disabled No retransmit on clock error 1 SE Slave enable 3 disabled SPI is configured as master 0 enabled SPI is configured as slave 1 SIE SPI interrupt enable 1 disable disable interrupts 0 enable enable interrupts 1 SSEN SPI enable 0 disable disable this module 0 enable enable this module 1 SPID SPI Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer 0x1C read-write n 0x0 0x0 DATA SOC bus bridge data 0 7 SPIINT_EN SPI Interrupt Enable 0x20 -1 read-write n 0x0 0x0 BP_DONE Byte packing BP_DONE interrupt enable 7 disable disable SOCBSTAT. BP_DONE interrupt 0 enable enable SOCBSTAT.BP_DONE interrupt 1 CYC_DONE_EN Cycle done CYC_DONE interrupt enable 5 disable disable SOCBSTAT.CYC_DONE interrupt 0 enable enable SOCBSTAT.CYC_DONE interrupt 1 LE_EN Leading edge detect LE interrupt enable 3 disable disable SOCBSTAT.LE interrupt 0 enable enable SOCBSTAT.LE interrupt 1 RDOFL_EN Read buffer overflow RDOFL interrupt enable 2 disable disable SOCBSTAT.RDOFL interrupt 0 enable enable SOCBSTAT.RDOFL interrupt 1 TE_EN Trailing edge detect TE interrupt enable 6 disable disable SOCBSTAT.TE interrupt 0 enable enable SOCBSTAT.TE interrupt 1 UCLK_EN Underclock UCLK interrupt enable 4 disable disable SOCBSTAT.UCLK interrupt 0 enable enable SOCBSTAT.UCLK interrupt 1 WRUFL_EN Write buffer underflow SOCBSTAT.WRUFL interrupt enable 8 disable disable SOCBSTAT.WRUFL interrupt 0 enable enable SOCBSTAT.WRUFL interrupt 1 SPISTAT SPI Status 0x14 read-write n 0x0 0x0 CURSTATE Raw status of the SOC bus bridge master state machine's 'current_state' register 12 2 IDLE IDLE 0 CSSETUP CSSETUP 1 TRANSFER TRANSFER 2 CSHOLD CSHOLD 3 CSWAIT CSWAIT 4 CKWAIT CKWAIT 5 MTRANS MTRANS 6 CSBEGIN CSBEGIN 7 CYC_DONE Cycle done (current transfer is complete) 5 not done No cycle done detected since this bit was cleared 0 completed Cycle done detected, write one to clear 1 LE Chip select leading edge detect 3 none No chip select assertion detected since this bit was cleared 0 detected Chip select assertion detected, write 1 to clear 1 RDOFL Read buffer overflow 2 none no read overflow since bit cleared 0 overflow read overflow detected, write 1 to clear 1 RXFULL Receive holding register in use 10 empty RX incoming holding register contains no valid data word 0 full RX incoming holding register contains a valid data word 1 SPI_INT SPI interrupt 0 none no interrupt 0 interrupt interrupt 1 TE Chip select trailing edge detect 6 none No chip select de-assertion detected since this bit was cleared 0 detected Chip select de-assertion was detected, write 1 to clear 1 TXFULL Transmit holding register in use 9 ready TX transmit holding register ready to accept data word 0 not ready TX transmit holding register in use and not ready 1 UCLK Underclock condition 4 none No underclock detected since this bit was cleared 0 detected Underclock condition detected, write 1 to clear 1 WRUFL Write buffer underflow 8 none No write buffer underflow detected since this bit was cleared 0 underflow Write buffer underflow detected, write one to clear 1 SYSCLK System and Clock Control SYSCLK 0x0 0x0 0x1000 registers n IRQ_SYSCLK 1 PLLCTL PLL Control Register 0x4 read-write n 0x0 0x0 PLLEN PLL enable 0 disable Disable PLL 0 enable Enable PLL 1 PLLFBDIV PLL Feedback Divider (divider = /[value + 2]) 7 8 /2 PLL feedback divider: /2 0 PLLINDIV PLL Input Divider (divider = /[value+2]) 2 4 /2 PLL input divider: /2 0 PLLOUTDIV PLL Output Divider (divider = /[value+1], 0 reserved) 16 3 /1 PLL output divider: /1 1 ROSCCTL Ring Oscillator Control Register 0x8 -1 read-write n 0x0 0x0 ROSCEN Ring Oscillator Enable 0 disable Disable Ring Oscillator 0 enable Enable Ring Oscillator 1 ROSCP Ring Oscillator Frequency Setting 1 1 28.7 MHz Set Ring Oscillator to 28.7 MHz 0 15.3 MHz Set Ring Oscillator to 15.3 MHz 1 10.7 MHz Set Ring Oscillator to 10.7 MHz 2 8.3 MHz Set Ring Oscillator to 8.3 MHz 3 SCCTL System Clock Control Register 0x0 read-write n 0x0 0x0 ACLKDIV ACLK divider 2 2 FCLK /1 ACLK = FCLK /1 0 FCLK /2 ACLK = FCLK /2 1 FCLK /4 ACLK = FCLK /4 2 FCLK /8 ACLK = FCLK /8 3 FCLK /16 ACLK = FCLK /16 4 FCLK /32 ACLK = FCLK /32 5 FCLK /64 ACLK = FCLK /64 6 FCLK /128 ACLK = FCLK /128 7 CLKIN FRCLK input clock select 0 1 ROSC Internal Ring Oscillator 0 CLKREF CLKREF input 1 EXTCLK External Clock Input 2 XTAL Crystal Driver XIN/XOUT Input 3 FCLK FCLK input clock select 7 FRCLK FCLK = FRCLK 0 PLLOUT FCLK = PLLOUT clock 1 HCLKDIV HCLK divider 5 1 FCLK /1 HCLK = FCLK /1 0 FCLK /2 HCLK = FCLK /2 1 FCLK /4 HCLK = FCLK /4 2 FCLK /8 HCLK = FCLK /8 3 XTALCTL Crystal Driver Control Register 0xC read-write n 0x0 0x0 XTALEN Enable XTAL driver 0 disable Disable XTAL Driver 0 enable Enable XTAL Driver 1 TIMERA Timer A Peripheral TIMERA 0x0 0x0 0x1000 registers n IRQ_TIMERA 8 DTGA0CTL Timer A dead-time generator control unit 0 0xA0 -1 read-write n 0x0 0x0 BYPASS bypass dead-time generation 7 disabled do not bypass dead-time generation 0 enabled bypass dead-time generation 1 INVHS Invert high-side output signal 5 disabled do not invert high-side output signal 0 enabled invert high-side output signal 1 INVLS Invert low-side output signal 4 disabled do not invert low-side output signal 0 enabled invert low-side output signal 1 OTP On-time preservation 6 disabled do not extend on time 0 enabled extend on time 1 DTGA0LED Timer A dead-time generator leading-edge delay counter unit 0 0xA4 read-write n 0x0 0x0 LED leading-edge delay counter 0 11 DTGA0TED Timer A dead-time generator trailing-edge delay counter unit 0 0xA8 read-write n 0x0 0x0 TED trailing-edge delay counter 0 11 DTGA1CTL Timer A dead-time generator control unit 1 0xB0 -1 read-write n 0x0 0x0 BYPASS bypass dead-time generation 7 disabled do not bypass dead-time generation 0 enabled bypass dead-time generation 1 INVHS Invert high-side output signal 5 disabled do not invert high-side output signal 0 enabled invert high-side output signal 1 INVLS Invert low-side output signal 4 disabled do not invert low-side output signal 0 enabled invert low-side output signal 1 OTP On-time preservation 6 disabled do not extend on time 0 enabled extend on time 1 DTGA1LED Timer A dead-time generator leading-edge delay counter unit 1 0xB4 read-write n 0x0 0x0 LED leading-edge delay counter 0 11 DTGA1TED Timer A dead-time generator trailing-edge delay counter unit 1 0xB8 read-write n 0x0 0x0 TED trailing-edge delay counter 0 11 DTGA2CTL Timer A dead-time generator control unit 2 0xC0 -1 read-write n 0x0 0x0 BYPASS bypass dead-time generation 7 disabled do not bypass dead-time generation 0 enabled bypass dead-time generation 1 INVHS Invert high-side output signal 5 disabled do not invert high-side output signal 0 enabled invert high-side output signal 1 INVLS Invert low-side output signal 4 disabled do not invert low-side output signal 0 enabled invert low-side output signal 1 OTP On-time preservation 6 disabled do not extend on time 0 enabled extend on time 1 DTGA2LED Timer A dead-time generator leading-edge delay counter unit 2 0xC4 read-write n 0x0 0x0 LED leading-edge delay counter 0 11 DTGA2TED Timer A dead-time generator trailing-edge delay counter unit 2 0xC8 read-write n 0x0 0x0 TED trailing-edge delay counter 0 11 DTGA3CTL Timer A dead-time generator control unit 3 0xD0 -1 read-write n 0x0 0x0 BYPASS bypass dead-time generation 7 disabled do not bypass dead-time generation 0 enabled bypass dead-time generation 1 INVHS Invert high-side output signal 5 disabled do not invert high-side output signal 0 enabled invert high-side output signal 1 INVLS Invert low-side output signal 4 disabled do not invert low-side output signal 0 enabled invert low-side output signal 1 OTP On-time preservation 6 disabled do not extend on time 0 enabled extend on time 1 DTGA3LED Timer A dead-time generator leading-edge delay counter unit 3 0xD4 read-write n 0x0 0x0 LED leading-edge delay counter 0 11 DTGA3TED Timer A dead-time generator trailing-edge delay counter unit 0 0xD8 read-write n 0x0 0x0 TED trailing-edge delay counter 0 11 TxCC0CTL timer capture and compare control unit 0 0x40 read-write n 0x0 0x0 CCEDG capture mode edge detect 0 1 hitolow high to low transition only 0 lowtohigh low to high transitions only 1 both both high to low and low to high transitions 2 CCINT capture and compare interrupt 2 none no interrupt detected 0 interrupt interrupt, write 1b to clear 1 CCINTEN capture and compare interrupt enable 3 disabled interrupt disabled 0 enabled interrupt enabled 1 CCMODE capture and compare mode 4 compare mode compare mode 0 capture mode capture mode 1 TxCC0CTR capture and compare counter unit 0 0x44 read-write n 0x0 0x0 CCCTR capture and compare counter value 0 15 TxCC1CTL timer capture and compare control unit 0 0x48 read-write n 0x0 0x0 CCEDG capture mode edge detect 0 1 hitolow high to low transition only 0 lowtohigh low to high transitions only 1 both both high to low and low to high transitions 2 CCINT capture and compare interrupt 2 none no interrupt detected 0 interrupt interrupt, write 1b to clear 1 CCINTEN capture and compare interrupt enable 3 disabled interrupt disabled 0 enabled interrupt enabled 1 CCMODE capture and compare mode 4 compare mode compare mode 0 capture mode capture mode 1 TxCC1CTR capture and compare counter unit 1 0x4C read-write n 0x0 0x0 TxCC2CTL timer capture and compare control unit 2 0x50 read-write n 0x0 0x0 TxCC2CTR capture and compare counter unit 2 0x54 read-write n 0x0 0x0 TxCC3CTL timer capture and compare control unit 3 0x58 read-write n 0x0 0x0 TxCC3CTR capture and compare counter unit 3 0x5C read-write n 0x0 0x0 TxCC4CTL timer capture and compare control unit 4 0x60 read-write n 0x0 0x0 TxCC4CTR capture and compare counter unit 4 0x64 read-write n 0x0 0x0 TxCC5CTL timer capture and compare control unit 5 0x68 read-write n 0x0 0x0 TxCC5CTR capture and compare counter unit 5 0x6C read-write n 0x0 0x0 TxCC6CTL timer capture and compare control unit 6 0x70 read-write n 0x0 0x0 TxCC6CTR capture and compare counter unit 6 0x74 read-write n 0x0 0x0 TxCC7CTL timer capture and compare control unit 7 0x78 read-write n 0x0 0x0 TxCC7CTR capture and compare counter unit 7 0x7C read-write n 0x0 0x0 TxCTL Timer Control Register 0x0 read-write n 0x0 0x0 CLK timer clock input source 9 HCLK HCLK 0 ACLK ACLK 1 CLKDIV timer clock divider 6 2 /1 divide by 1 0 /2 divide by 2 1 /4 divide by 4 2 /8 divide by 8 3 /16 divide by 16 4 /32 divide by 32 5 /64 divide by 64 6 /128 divide by 128 7 CLR Timer clear 2 clear Clear Timer, hold in reset, set SYNC_OUT 0 noclear Do not clear timer, clear SYNC_OUT 1 DTGCLK DTG clock select 13 CLK DTG uses clock selected by TxTCL.CLK 0 CLKDIV DTG uses clock selected by TxCTL.CLKDIV 1 INT Timer interrupt 4 interrupt interrupt flag, write 1 to clear 0 noint No interrupt 1 INTEN Timer interrupt enable 5 enabled timer interrupt enabled 0 disabled timer interrupt disabled 1 MODE timer mode 10 1 disabled timer disabled 0 up up mode 1 updown up/down mode 2 PRDL Timer Period Latch 0 period Latch timer values counting up at TxPRD-1 0 wrap Latch timer values when counting down to 1 1 SS Timer single shot 3 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 single Single shot mode 1 TxCTR timer counter 0x8 read-only n 0x0 0x0 CTR timer counter value 0 15 TxPRD timer period 0x4 read-write n 0x0 0x0 PERIOD timer period value 0 15 TIMERB Timer B Peripheral TIMERB 0x0 0x0 0x1000 registers n IRQ_TIMERB 10 DTGB0CTL Timer B dead-time generator control unit 0 0xA0 -1 read-write n 0x0 0x0 BYPASS bypass dead-time generation 7 disabled do not bypass dead-time generation 0 enabled bypass dead-time generation 1 INVHS Invert high-side output signal 5 disabled do not invert high-side output signal 0 enabled invert high-side output signal 1 INVLS Invert low-side output signal 4 disabled do not invert low-side output signal 0 enabled invert low-side output signal 1 OTP On-time preservation 6 disabled do not extend on time 0 enabled extend on time 1 DTGB0LED Timer B dead-time generator leading-edge delay counter unit 0 0xA4 read-write n 0x0 0x0 LED leading-edge delay counter 0 11 DTGB0TED Timer B dead-time generator trailing-edge delay counter unit 0 0xA8 read-write n 0x0 0x0 TED trailing-edge delay counter 0 11 TxCC0CTL timer capture and compare control unit 0 0x40 read-write n 0x0 0x0 CCEDG capture mode edge detect 0 1 hitolow high to low transition only 0 lowtohigh low to high transitions only 1 both both high to low and low to high transitions 2 CCINT capture and compare interrupt 2 none no interrupt detected 0 interrupt interrupt, write 1b to clear 1 CCINTEN capture and compare interrupt enable 3 disabled interrupt disabled 0 enabled interrupt enabled 1 CCMODE capture and compare mode 4 compare mode compare mode 0 capture mode capture mode 1 TxCC0CTR capture and compare counter unit 0 0x44 read-write n 0x0 0x0 CCCTR capture and compare counter value 0 15 TxCC1CTL timer capture and compare control unit 1 0x48 read-write n 0x0 0x0 TxCC1CTR capture and compare counter unit 1 0x4C read-write n 0x0 0x0 TxCC2CTL timer capture and compare control unit 2 0x50 read-write n 0x0 0x0 TxCC2CTR capture and compare counter unit 2 0x54 read-write n 0x0 0x0 TxCC3CTL timer capture and compare control unit 3 0x58 read-write n 0x0 0x0 TxCC3CTR capture and compare counter unit 3 0x5C read-write n 0x0 0x0 TxCTL Timer Control Register 0x0 read-write n 0x0 0x0 CLK timer clock input source 9 HCLK HCLK 0 ACLK ACLK 1 CLKDIV timer clock divider 6 2 /1 divide by 1 0 /2 divide by 2 1 /4 divide by 4 2 /8 divide by 8 3 /16 divide by 16 4 /32 divide by 32 5 /64 divide by 64 6 /128 divide by 128 7 CLR Timer clear 2 clear Clear Timer, hold in reset, set SYNC_OUT 0 noclear Do not clear timer, clear SYNC_OUT 1 DTGCLK DTG clock select 13 CLK DTG uses clock selected by TxTCL.CLK 0 CLKDIV DTG uses clock selected by TxCTL.CLKDIV 1 INT Timer interrupt 4 interrupt interrupt flag, write 1 to clear 0 noint No interrupt 1 INTEN Timer interrupt enable 5 enabled timer interrupt enabled 0 disabled timer interrupt disabled 1 MODE timer mode 10 1 disabled timer disabled 0 up up mode 1 updown up/down mode 2 PRDL Timer Period Latch 0 period Latch timer values counting up at TxPRD-1 0 wrap Latch timer values when counting down to 1 1 SS Timer single shot 3 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 single Single shot mode 1 TxCTR timer counter 0x8 read-only n 0x0 0x0 CTR timer counter value 0 15 TxPRD timer period 0x4 read-write n 0x0 0x0 PERIOD timer period value 0 15 TIMERC Timer C Peripheral TIMERC 0x0 0x0 0x1000 registers n IRQ_TIMERC 11 DTGC0CTL Timer C dead-time generator control unit 0 0xA0 -1 read-write n 0x0 0x0 BYPASS bypass dead-time generation 7 disabled do not bypass dead-time generation 0 enabled bypass dead-time generation 1 INVHS Invert high-side output signal 5 disabled do not invert high-side output signal 0 enabled invert high-side output signal 1 INVLS Invert low-side output signal 4 disabled do not invert low-side output signal 0 enabled invert low-side output signal 1 OTP On-time preservation 6 disabled do not extend on time 0 enabled extend on time 1 DTGC0LED Timer C dead-time generator leading-edge delay counter unit 0 0xA4 read-write n 0x0 0x0 LED leading-edge delay counter 0 11 DTGC0TED Timer C dead-time generator trailing-edge delay counter unit 0 0xA8 read-write n 0x0 0x0 TED trailing-edge delay counter 0 11 TxCC0CTL timer capture and compare control unit 0 0x40 read-write n 0x0 0x0 CCEDG capture mode edge detect 0 1 hitolow high to low transition only 0 lowtohigh low to high transitions only 1 both both high to low and low to high transitions 2 CCINT capture and compare interrupt 2 none no interrupt detected 0 interrupt interrupt, write 1b to clear 1 CCINTEN capture and compare interrupt enable 3 disabled interrupt disabled 0 enabled interrupt enabled 1 CCMODE capture and compare mode 4 compare mode compare mode 0 capture mode capture mode 1 TxCC0CTR capture and compare counter unit 0 0x44 read-write n 0x0 0x0 CCCTR capture and compare counter value 0 15 TxCC1CTL timer capture and compare control unit 1 0x48 read-write n 0x0 0x0 TxCC1CTR capture and compare counter unit 1 0x4C read-write n 0x0 0x0 TxCTL Timer Control Register 0x0 read-write n 0x0 0x0 CLK timer clock input source 9 HCLK HCLK 0 ACLK ACLK 1 CLKDIV timer clock divider 6 2 /1 divide by 1 0 /2 divide by 2 1 /4 divide by 4 2 /8 divide by 8 3 /16 divide by 16 4 /32 divide by 32 5 /64 divide by 64 6 /128 divide by 128 7 CLR Timer clear 2 clear Clear Timer, hold in reset, set SYNC_OUT 0 noclear Do not clear timer, clear SYNC_OUT 1 DTGCLK DTG clock select 13 CLK DTG uses clock selected by TxTCL.CLK 0 CLKDIV DTG uses clock selected by TxCTL.CLKDIV 1 INT Timer interrupt 4 interrupt interrupt flag, write 1 to clear 0 noint No interrupt 1 INTEN Timer interrupt enable 5 enabled timer interrupt enabled 0 disabled timer interrupt disabled 1 MODE timer mode 10 1 disabled timer disabled 0 up up mode 1 updown up/down mode 2 PRDL Timer Period Latch 0 period Latch timer values counting up at TxPRD-1 0 wrap Latch timer values when counting down to 1 1 SS Timer single shot 3 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 single Single shot mode 1 TxCTR timer counter 0x8 read-only n 0x0 0x0 CTR timer counter value 0 15 TxPRD timer period 0x4 read-write n 0x0 0x0 PERIOD timer period value 0 15 TIMERD Timer D Peripheral TIMERD 0x0 0x0 0x1000 registers n I_TIMERD Timer Interrupt Register 12 DTGD0CTL Timer A dead-time generator control unit 0 0xA0 -1 read-write n 0x0 0x0 BYPASS bypass dead-time generation 7 disabled do not bypass dead-time generation 0 enabled bypass dead-time generation 1 INVHS Invert high-side output signal 5 disabled do not invert high-side output signal 0 enabled invert high-side output signal 1 INVLS Invert low-side output signal 4 disabled do not invert low-side output signal 0 enabled invert low-side output signal 1 OTP On-time preservation 6 disabled do not extend on time 0 enabled extend on time 1 DTGD0LED Timer A dead-time generator leading-edge delay counter unit 0 0xA4 read-write n 0x0 0x0 LED leading-edge delay counter 0 11 DTGD0TED Timer A dead-time generator trailing-edge delay counter unit 0 0xA8 read-write n 0x0 0x0 TED trailing-edge delay counter 0 11 TxCC0CTL timer capture and compare control unit 0 0x40 read-write n 0x0 0x0 CCEDG capture mode edge detect 0 1 hitolow high to low transition only 0 lowtohigh low to high transitions only 1 both both high to low and low to high transitions 2 CCINT capture and compare interrupt 2 none no interrupt detected 0 interrupt interrupt, write 1b to clear 1 CCINTEN capture and compare interrupt enable 3 disabled interrupt disabled 0 enabled interrupt enabled 1 CCMODE capture and compare mode 4 compare mode compare mode 0 capture mode capture mode 1 TxCC0CTR capture and compare counter unit 0 0x44 read-write n 0x0 0x0 CCCTR capture and compare counter value 0 15 TxCC1CTL timer capture and compare control unit 1 0x48 read-write n 0x0 0x0 TxCC1CTR capture and compare counter unit 1 0x4C read-write n 0x0 0x0 TxCTL Timer Control Register 0x0 read-write n 0x0 0x0 CLK timer clock input source 9 HCLK HCLK 0 ACLK ACLK 1 CLKDIV timer clock divider 6 2 /1 divide by 1 0 /2 divide by 2 1 /4 divide by 4 2 /8 divide by 8 3 /16 divide by 16 4 /32 divide by 32 5 /64 divide by 64 6 /128 divide by 128 7 CLR Timer clear 2 clear Clear Timer, hold in reset, set SYNC_OUT 0 noclear Do not clear timer, clear SYNC_OUT 1 DTGCLK DTG clock select 13 CLK DTG uses clock selected by TxTCL.CLK 0 CLKDIV DTG uses clock selected by TxCTL.CLKDIV 1 INT Timer interrupt 4 interrupt interrupt flag, write 1 to clear 0 noint No interrupt 1 INTEN Timer interrupt enable 5 enabled timer interrupt enabled 0 disabled timer interrupt disabled 1 MODE timer mode 10 1 disabled timer disabled 0 up up mode 1 updown up/down mode 2 PRDL Timer Period Latch 0 period Latch timer values counting up at TxPRD-1 0 wrap Latch timer values when counting down to 1 1 SS Timer single shot 3 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 continuous Continuous mode 0 single Single shot mode 1 TxCTR timer counter 0x8 read-only n 0x0 0x0 CTR timer counter value 0 15 TxPRD timer period 0x4 read-write n 0x0 0x0 PERIOD timer period value 0 15 UART UART UART 0x0 0x0 0x1000 registers n IRQ_UART 16 UARTDL_H UART divisor latch high byte 0x2C read-write n 0x0 0x0 DL_H Divisor value, high byte 0 7 UARTDL_L UART divisor latch low byte 0x28 read-write n 0x0 0x0 DL_L RX register data available interrupt enable 0 7 UARTFCTL FIFO control 0x20 -1 read-write n 0x0 0x0 FEN FIFO enable 0 disabled disable RX, TX FIFO 0 enabled enable RX, TX FIFO 1 RXFRESET RX FIFO reset 1 no action no action 0 clear clear RX FIFO, cleared on read 1 RXFT RX FIFO Theshold 6 1 1 1 byte in FIFO 0 4 4 bytes in FIFO 1 8 8 bytes in FIFO 2 14 14 bytes in FIFO 3 TXFRESET RX FIFO reset 2 no action no action 0 clear clear TX FIFO, cleared on read 1 UARTFD_F UART fractional divisor value 0x38 read-write n 0x0 0x0 FRAC Fractional divisor value 0 7 UARTFSTAT UART FIFO status 0x40 -1 read-write n 0x0 0x0 RXFE RX FIFO empty 2 not empty RX FIFO not empty 0 empty RX FIFO empty 1 RXFF RX FIFO full 3 not full RX FIFO not full 0 full RX FIFO full 1 TXFE TX FIFO empty 0 not empty TX FIFO not empty 0 empty TX FIFO empty 1 TXFF TX FIFO full 1 not full TX FIFO not full 0 full TX FIFO full 1 UARTIEN UART interrupt enable 0x4 read-write n 0x0 0x0 MSINTEN Model Status interrupt enable 3 disable disable interrupt 0 enable enable interrupt 1 RSINTEN Receive interrupt enable 2 disable disable interrupt 0 enable enable interrupt 1 RXINTEN RX register data available interrupt enable 0 disable disable interrupt 0 enable enable interrupt 1 TXINTEN TX register data available interrupt enable 1 disable disable interrupt 0 enable enable interrupt 1 UARTIE_R UART interrupt enable remapped 0x24 read-write n 0x0 0x0 MSINTEN Modem status interrupt enable 3 disabled disable interrupt 0 enabled enable interrupt 1 RSINTEN Receive interrupt enable 2 disabled disable interrupt 0 enabled enable interrupt 1 RXINTEN RX register data available interrupt enable 0 disabled disable interrupt 0 enabled enable interrupt 1 TXINTEN TX register data available interrupt enable 1 disabled disable interrupt 0 enabled enable interrupt 1 UARTII UART interrupt identification 0x8 -1 read-write n 0x0 0x0 UARTINT UART interrupt 0 disable disable interrupt 0 enable enable interrupt 1 UARTINTID UART interrupt type 1 2 modem status modem status 0 TX hold register empty TX hold register empty 1 RX data available RX data available 2 RX line status RX line status 3 Timeout Timeout 6 UARTLC UART Line Control 0xC read-write n 0x0 0x0 BPC Bit per character 0 1 5 5 bits 0 6 6 bits 1 7 7 bits 2 8 8 bits 3 EPS Parity type 4 odd generate ODD parity 0 even generate EVEN parity 1 PEN Parity enable 3 disabled parity disabled 0 enabled parity enabled 1 SB Break control 6 normal normal operation 0 0 force TX to 0 1 SP Stick parity 5 disable disable 0 enable enable 1 STB Stop bits 2 1 1 stop bit 0 2 2 stop bits (1.5 if BPC=00b) 1 UARTLS UART Line Status 0x14 -1 read-write n 0x0 0x0 RXBE RX break error 4 cleared error cleared 0 error entry on top of RX FIFO has break error, cleared on read 1 RXDR RX data ready 0 empty RX FIFO empty 0 not empty At least one entry in RX FIFO 1 RXE RX FIFO error 7 no error no error in RX FIFO 0 error At least one parity, framing or break error active in FIFO 1 RXFE RX framing error 3 cleared error cleared 0 error entry on top of RX FIFO has framing error, cleared on read 1 RXOE RX overrun error 1 cleared error cleared 0 full RX FIFO full and last entry overwritten, cleared on read 1 RXPE RX parity error 2 cleared error cleared 0 error entry on top of RX FIFO has parity error, cleared on read 1 TCFE TX FIFO empty 5 cleared error cleared 0 error TX FIFO is empty 1 TXE TX empty 6 cleared error cleared 0 error TX shift register and TX FIFO are empty 1 UARTRXTX UART receive/transmit FIFO 0x0 read-write n 0x0 0x0 RXTX Receive and Transmit FIFO buffer (read: RX FIFO, write: TX FIFO) 0 7 WDT Watchdog Timer WDT 0x0 0x0 0x1000 registers n IRQ_WDT 2 WDTCDV Watchdog Timer Count-down Value Register 0x4 -1 read-write n 0x0 0x0 KEY WDTCTL register key 24 7 RSTVALUE 24b WDT count-down value 0 23 WDTCTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 KEY WDTCTL register key 24 7 WDTCLKDIV Watchdog Timer Input Clock Divider 6 3 /2 WDT clock divider: /2 0 /4 WDT clock divider: /4 1 /2048 WDT clock divider: /2048 10 /4096 WDT clock divider: /4096 11 /8192 WDT clock divider: /8192 12 /16384 WDT clock divider: /16384 13 /32768 WDT clock divider: /32768 14 /65536 WDT clock divider: /65536 15 /8 WDT clock divider: /8 2 /16 WDT clock divider: /16 3 /32 WDT clock divider: /32 4 /64 WDT clock divider: /64 5 /128 WDT clock divider: /128 6 /256 WDT clock divider: /256 7 /512 WDT clock divider: /512 8 /1024 WDT clock divider: /1024 9 WDTCLKSEL Watchdog Timer Input Clock Select 10 FRCLK Watchdog timer input clock: FRCLK 0 FCLK Watchdog timer input clock: FCLK 1 WDTCTRRST Watchdog Timer Counter Reset 0 2 key WDTCTL Reset Key 5 WDTINT Watchdog Interval Timer Interrupt Flag 4 read-only clear Watchdog timer interrupt flag clear 0 set Watchdog timer interrupt flag set 1 WDTINTEN Watchdog Interval Timer Interrupt Enable 3 disabled Watchdog timer interval interrupt disabled 0 enabled Watchdog timer interval interrupt enabled 1 WDTRESETEN Watchdog Timer Device Reset Enable 5 disabled Watchdog timer device reset disabled 0 enabled Watchdog timer device reset enabled 1 WRBUSY WDT register write busy 11 read-only not busy Watchdog timer register write not busy 0 busy Watchdog timer register write busy 1 WDTCTR Watchdog Timer Counter Register 0x8 -1 read-only n 0x0 0x0